LISA-U1 series - System Integration Manual
3G.G2-HW-10002-3
Preliminary
System description
Page 11 of 125
1.3
Pin-out
Table 2 lists the pin-out of the LISA-U1 series modules, with pins grouped by function.
Function
Pin
No
I/O
Description
Remarks
Power
VCC
61, 62, 63
I
Module Supply
Clean and stable supply is required: low ripple and
low voltage drop must be guaranteed.
Voltage provided has to be always above the
minimum limit of the operating range.
Consider that there are large current spikes in
connected mode, when a GSM call is enabled.
VCC
pins are internally connected, but all the
available pads must be connected to the external
supply in order to minimize power loss due to
series resistance.
See section 1.5.2
GND
1, 3, 6, 7,
8, 17, 25,
28, 29, 30,
31, 32, 33,
34, 35, 36,
37, 38, 60,
64, 65, 66,
67, 69, 70,
71, 72, 73,
75, 76
N/A
Ground
GND
pins are internally connected but a good
(low impedance) external ground connection can
improve RF performance: all
GND
pins must be
externally connected to ground.
V_BCKP
2
I/O
Real Time Clock supply
input/output
V_BCKP
= 2.3 V (typical) generated by the module
when
VCC
supply voltage is within valid operating
range.
See section 1.5.4
V_INT
4
O
Digital I/O Interfaces
supply output
V_INT
= 1.8V (typical) generated by the module
when it is switched-on and the
RESET_N
(external
reset input pin) is not forced to the low level.
See section 1.5.5
VSIM
50
O
SIM supply output
VSIM
= 1.80 V typical or 2.90 V typical generated
by the module according to the SIM card type.
See section 1.8
RF
ANT
68
I/O
RF antenna interface
50 nominal impedance.
See section 1.7, section 2.4 and section 2.2.1.1
SIM
SIM_IO
48
I/O
SIM data
Internal 4.7 k pull-up to
VSIM
.
Must meet SIM specifications.
See section 1.8
SIM_CLK
47
O
SIM clock
Must meet SIM specifications.
See section 1.8
SIM_RST
49
O
SIM reset
Must meet SIM specifications.
See section 1.8
SPI
SPI_MISO
57
O
SPI Data Line.
Master Input,
Slave Output
Module Output: module runs as an SPI slave.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
Idle high.
See section 1.9.4
SPI_MOSI
56
I
SPI Data Line.
Master Output,
Slave Input
Module Input: module runs as an SPI slave.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
Idle high.
Internal active pull-up to
V_INT
(1.8 V) enabled.
See section 1.9.4
SPI_SCLK
55
I
SPI Serial Clock.
Master Output,
Slave Input
Module Input: module runs as an SPI slave.
Idle low (CPOL=0).
Internal active pull-down to
GND
enabled.
See section 1.9.4
