LISA-U1 series - System Integration Manual
3G.G2-HW-10002-3
Preliminary
System description
Page 31 of 125
Reference
Description
Part Number - Manufacturer
C1
100 µF Tantalum Capacitor
GRM43SR60J107M - Murata
R2
4.7 k
Ω
Resistor 0402 5% 0.1 W
RC0402JR-074K7L - Yageo Phycomp
C2
70 mF Capacitor
XH414H-IV01E - Seiko Instruments
Table 9: Example of components for V_BCKP buffering
If longer buffering time is required to allow the time reference to run during a disconnection of the
VCC
supply,
then an external battery can be connected to
V_BCKP
pin. The battery should be able to provide a 2.3 V
nominal voltage and must never exceed the maximum operating voltage for
V_BCKP
. The connection of the
battery to
V_BCKP
should be done with a suitable series resistor for a rechargeable battery, or with an
appropriate series diode for a non-rechargeable battery. The purpose of the series resistor is to limit the battery
charging current due to the battery specifications, and also to allow a fast rise time of the voltage value at the
V_BCKP
pin after the
VCC
supply has been provided. The purpose of the series diode is to avoid a current flow
from the module
V_BCKP
pin to the non-rechargeable battery.
1.5.5
Interface supply (V_INT)
The same voltage domain used internally to supply the digital interfaces is also available on the
V_INT
pin. The
internal regulator that generates the
V_INT
supply is a switching step down converter that is directly supplied
from
VCC
. The voltage regulator output is set to 1.8 V (typical) when the module is switched on and is disabled
when the module is switched off or when the
RESET_N
pin is forced the low level. The switching regulator
operates in Pulse Width Modulation (PWM) for high output current mode but automatically switches to Pulse
Frequency Modulation (PFM) at low output loads for greater efficiency, e.g. when the module is in idle mode
between paging periods.
Name
Description
Remarks
V_INT
Digital Interfaces supply output
V_INT
= 1.8V (typical) generated by the module when it is
switched-on and the
RESET_N
(external reset input pin) is
not forced to the low level.
V_INT
is the internal supply for digital interfaces.
The user may draw limited current from this supply rail.
Table 10: Interface supply pin
The
V_INT
pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher
protection level could be required if the line is externally accessible on the application board. Higher
protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor
array) on the line connected to this pin.
Since it supplies internal digital circuits (see Figure 4),
V_INT
is not suited to directly supply any sensitive analog
circuit: the voltage ripple can range from 15 mVpp during active mode (PWM), to 70 mVpp in idle mode (PFM).
V_INT
can be used to supply external digital circuits operating at the same voltage level as the digital
interface pins, i.e. 1.8 V (typical). It is not recommended to supply analog circuitry without adequate
filtering for digital noise.
Don’t apply loads which might exceed the limit for maximum available current from
V_INT
supply, as
this can cause malfunctions in internal circuitry supplies to the same domain. The detailed electrical
characteristics are described in the
LISA-U1 series
Data Sheet
