Ublox BMD-340-EVAL, Руководство пользователя

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BMD-34x-EVAL User Guide Rev 2.0
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6.9 External Segger J- Link™ Debug Interface
External target hardware can be connected to J3 for firmware programming and debug. The Segger
debug interface is implemented as shown in Figure 12. J3 is implemented with a 2x5 10-pin header on
0.05” centers.
Figure 12 – External J-Link Debug Interface
In order to enable the external J-Link connection, ensure the following are implemented on the target
hardware:
• EXT_VTG is used by the debug interface as an input to sense power applied to the external circuit.
Only voltages of ~3.0V to ~3.3V are supported. Other operating voltages require the use of an
external J-Link Debug Probe. Connect EXT_VTG to the BMD-34x power supply (VCC) on the target
hardware.
•
EXT_GND_DETECT is used by the debug interface to detect the presence of external target
hardware. Connect EXT_GND_DETECT to GND on the target hardware.
• Connect GND to GND on the target hardware.
• Connect EXT_SWDIO and EXT_SWCLK to SWDIO and SWDCLK on the target BMD-3xx, respectively.
•
(Optional) Connect EXT_SWO and/or EXT_RESETn on the target BMD-3xx, respectively.
•
Connect external power to the target hardware, then connect the BMD-34x Evaluation Board to
USB.
• At this point, the debug interface will interact with the target hardware instead of the on-board
BMD-3xx.