u-blox JODY-W2, Руководство по системной интеграции

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JODY-W2 - System integration manual
UBX-18068879 - R14 Design-in Page 28 of 84
C1 - Public
2.4 Data communication interfaces
SDIO 3.0
As the SDIO 3.0 bus in JODY-W2 modules can support a clock frequency up to 208 MHz, special care
must be taken to minimize potential EMI issues and ensure that the signal integrity requirements are
met. The signals should be routed with a single ended impedance of 50
Ω
.
It is recommended to route all signals in the bus with the same length and have appropriate grounding
in the surrounding layers; total bus length should also be minimized. The layout of the SDIO bus should
be done so that crosstalk with other parts of the circuit is minimized providing adequate isolation
between the signals, clock, and surrounding busses/traces.
Figure 8 shows the suggested application schematic for the SDIO bus in JODY-W2 modules.
Figure 8: SDIO application schematic
☞
A small value capacitor in the range of few pF should be considered in parallel to SDIO_CLK as
EMI debug option and signal termination. This capacitor should be placed as close as possible
to the JODY-W2 clock input pin and can be assembled only for EMI purpose. The capacitor
value adds to total line capacitance and must not exceed total allowed capacitance to avoid
violating clock rise and fall timing specifications.
Table 19 summarizes the electrical requirements of the bus.
Signal Group Parameter Min. Typ. Max. Unit
CLK, CMD, DAT[0:3] Single ended impedance,
𝑍
0
50
Ω
CLK, CMD, DAT[0:3] Impedance control
𝑍
0
− 10% 𝑍
0
𝑍
0
+ 10%
Ω
DAT[0:3] Pull-Up range, Rdat 10 47 100 k
Ω
CMD Pull-Up range, Rcmd 10 10 50 k
Ω
CLK, CMD, DAT[0:3] Series termination (Host side), Rterm
6
0 22
Ω
CLK, CMD, DAT[0:3] Bus length
7
100 mm
CMD, DAT[0:3] Bus skew length mismatch to CLK -3 +3 mm
CLK Center to center CLK to other SDIO signals
8
4*W
CMD, DAT[0:3] Center to center between signals
11
3*W
Table 19: SDIO bus requirements
6
Series termination values larger than typical recommended only for addressing EMI issues.
7
Routing should minimize the total bus length.
8
Center to center spacing requirement can be ignored for up to 10 mm of routed length to accommodate BGA escape.