EVA-M8E - Hardware Integration Manual
UBX-15028542 - R05
Contents
Page 9 of 44
Production Information
•
Single supply voltage for
VCC
and
VCC_IO
, use of a backup supply
see Appendix, Figure 17
☞
For description of the different power operating modes, see the EVA-M8E Data Sheet [1].
2.2
Interfaces
The EVA-M8E module provides UART, SPI, DDC (I
2
C compliant) interfaces for communication with a
host CPU. A USB interface is also available on specific pins (see section 2.2.5). Additionally, an SQI
interface is available for connecting the EVA-M8E module with a mandatory external flash memory.
An extra dedicated DDC (I
2
C compliant) interface is reserved to communicate with an external Inertial
Measurement Unit, which includes 3D accelerometer and 3D gyroscope sensors.
The UART, SPI and DDC pins are supplied by
VCC_IO
and operate at this voltage level.
Four dedicated pins can be configured as either 1 x UART and 1 x DDC or a single SPI interface
selectable by
D_SEL
pin. Table 1 below provides the port mapping details.
Pin 32 (D_SEL) = “high” (left open)
Pin 32 (D_SEL) = “Low” (connected to GND)
UART TXD
SPI MISO
UART RXD
SPI MOSI
DDC SCL
SPI CLK
DDC SDA
SPI CS_N
Table 1: Communication Interfaces overview
☞
It is not possible to use the SPI interface simultaneously with the DDC or UART interface.
☞
For debugging purposes, it is recommended to have a second interface e.g. USB available that is
independent from the application and accessible via test-points.
For each interface, a dedicated pin can be defined to indicate that data is ready to be transmitted.
The TX Ready signal indicates that the receiver has data to transmit. A listener can wait on the TX
Ready signal instead of polling the DDC or SPI interfaces. The UBX-CFG-PRT message lets you
configure the polarity and the number of bytes in the buffer before the TX Ready signal goes active.
The TX Ready function is disabled by default.
☞
The TX Ready functionality can be enabled and configured by proper AT commands sent to the
involved u-blox cellular module supporting the feature. For more information see the GPS
Implementation and Aiding Features in u-blox wireless modules [5].
☞
The TX Ready feature is supported on version LEON FW 7.xx and LISA-U2 01S and above.
2.2.1
UART interface
A UART interface is available for serial communication to a host CPU. The UART interface supports
configurable data rates with the default at 9600 baud. Signal levels are related to the
VCC_IO
supply
voltage. An interface based on RS232 standard levels (+/- 7 V) can be realized using level shifter ICs
such as the Maxim MAX3232.
Hardware handshake signals and synchronous operation are not supported.
A signal change on the UART RX pin can also be used to wake up the receiver in Power Save Mode (see
the u-blox 8 / u-blox M8 Receiver Description Including Protocol Specification [2]).
☞
Designs must allow access to the UART and the
SAFEBOOT_N
pin for future service, updates, and
reconfiguration.
