EVA-M8E - Hardware Integration Manual
UBX-15028542 - R05
Contents
Page 10 of 44
Production Information
2.2.2
Display Data Channel (DDC) Interface
An I
2
C compliant DDC interface is available for communication with an external host CPU or u-blox
cellular modules. The interface can be operated in slave mode only. The DDC protocol and electrical
interface are fully compatible with Fast-Mode of the I
2
C industry standard. Since the maximum SCL
clock frequency is 400 kHz, the maximum transfer rate is 400 kb/s.
The SCL and SDA pins have internal pull-up resistors sufficient for most applications. However,
depending on the speed of the host and the load on the DDC lines additional external pull-up resistors
might be necessary. For speed and clock frequency, see the EVA-M8E Data Sheet [1].
☞
To make use of DDC interface, the
D_SEL
pin has to be left open.
For more information about DDC implementation, refer to the u-blox 8 / u-blox M8 Receiver
Description Including Protocol Specification [2].
2.2.3
SPI Interface
The SPI interface can be used to provide a serial communication with a host CPU. If the SPI interface
is used, UART and DDC are deactivated, because they share the same pins.
☞
To make use of the SPI interface, the
D_SEL
pin has to be connected to GND.
2.2.4
Integrated IMU Sensor Interface
A dedicated I
2
C compliant DDC interface is available and reserved for communication with an external
Inertial Measurement Unit, which employs 3D accelerometer and 3D gyroscope sensors. The interface
can be operated in master mode only. The DDC protocol and electrical interface are fully compatible
with Fast-Mode of the I
2
C industry standard. Since the maximum SCL clock frequency is 400 kHz,
thus the maximum transfer rate is 400 kbit/s.
The DDC interface is I
2
C Fast Mode compliant. For timing parameters, consult the I
2
C standard.
☞
The maximum bit rate is 400 kb/s. The interface stretches the clock when slowed down while
serving interrupts, so real bit rates may be slightly lower.
☞
Supply needs to be derived from VCC_IO
☞
For a detailed list of supported sensor modules, see Appendix B.8.
2.2.5
USB interface
The USB interface of the EVA-M8E module supports the full-speed data rate of 12
Mbit/s. It is
compatible to the USB 2.0 FS standard. The interface requires some external components in order to
implement the physical characteristics required by the USB 2.0 specification. Figure 2 shows the
interface pins and additional external components. In order to comply with USB specifications, VBUS
must be connected through a LDO (U2) to pin
VDD_USB
of the EVA-M8E receiver. This ensures that
the internal 1.5
k
Ω
pull-up resistor on
USB_DP
gets disconnected when the USB host shuts down
VBUS.
Depending on the characteristics of the LDO (U2), for a self-powered design it is recommended to add
a pull-down resistor (R8) at its output to ensure
VDD_USB
does not float if a USB cable is not
connected, i.e. when VBUS is not present. In USB
self-powered
mode, the power supply (
VCC
) can be
turned off and the digital block is not powered. In this case, since VBUS is still available, the USB host
would still receive the signal indicating that the device is present and ready to communicate. This
should be avoided by disabling the LDO (U1) using the enable signal (EN) of the VCC-LDO or the output
of a voltage supervisor.
