u-blox AMY-5M, Руководство по оборудованию, Страница: 22 / 54

AMY-5M - Hardware Integration Manual
GPS.G5-MS5-08207-A3 Preliminary Design-in
Page 22 of 54
u-blox 5 M odule EEPROM
SDA2
SCL2
SDA
SCL
VDD
VDD_IO
R20
VDD
R21
Exte rnal CPU / Host
SDA SCL
VDD
A0
A1
A2
WP
}
000
Figure 14: Connecting external serial I
2
C memory used by external host (see data sheet for exact pin orientation)
2.3.3.3 DDC troubleshooting
Consider the following questions when implementing DDC in designs:
Is there a stable supply voltage Vdd? Often, external I 2 C devices (like I 2 C masters or monitors) must be
provided with Vdd.
Are appropriate termination resistances attached between SDA, SCL and Vdd? The voltage level on SDA and
SCL must be Vdd as long as the bus is idle and drop near GND if shorted to GND. [Note: Very few I
2
C
masters exist which drive SCL high and low, i.e. the SCL line is not open-drain. In this case, a termination
resistor is not needed and SCL cannot be pulled low. These masters will not work together with other
masters (as they have no multi-master support) and may not be used with devices which stretch SCL during
transfers.]
Are SDA and SCL mixed up? This may accidentally happen e.g. when connecting I
2
C buses with cables or
connectors.
Do all I
2
C devices support the I
2
C supply voltage used on the bus?
Do all I
2
C devices support the maximum SCL clock rate used on the bus?
If more than one I2C master is connected to the bus: do all masters provide multi-master support?
Are the high and low level voltages on SDA and SCL correct during I2C transfers? The I
2
C standard defines
the low level threshold with 0.3 Vcc, the high level threshold with 0.7 Vcc. Modifying the termination
resistance Rp, the serial resistors Rs or lowering the SCL clock rate could help here.
Are there spikes or noise on SDA, SCL or even Vdd? They may result from interferences from other
components or because the capacitances Cp and/or Cc are too high. The effects can often be reduced by
using shorter interconnections.
For more information about DDC implementation refer to the u-blox 5 Receiver Description including
Protocol Specification [1].