TYAN S1590, Руководство пользователя

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Chapter 3
BIOS Configuration
Chipset Features Setup - Default Settings Chart
Bank 0/1, 2/3, 4/5 DRAM Timing
The system board designer must select the proper value for these fields,
according to the specifications of the installed DRAM chips. Turbo mode
reduces CAS access time by 1 clock tick.
SDRAM Cycle Length
This field sets the CAS latency timing.
DRAM Read Pipeline
Select Enabled to pipeline reads from system memory. Pipelining improves
system performance.
Cache Rd+CPU Wt Pipeline
Select Enabled to pipeline reads from cache memory and writes from the CPU.
Pipelining improves system performance.
Cache Timing
For a secondary cache of one bank, select Faster. For a secondary cache of
two banks, select Fastest.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to
C7FFFh, resulting in better video performance. However, if any program writes
Se tting Option BIOS De fault Se tup De fault
Bank 0/1 DRA M Timing FP/EDO 70ns FP/EDO 60ns
Bank 2/3 DRA M Timing FP/EDO 70ns FP/EDO 60ns
Bank 4/5 DRA M Timing SDRA M 10ns SDRA M 8ns
SDRA M Cy cle Length 3 3
DRA M Read Pipeline Dis abled Enabled
Cac he Rd+CPU Wt Pipeline Dis abled Enabled
Cac he Timing Fas t Fas t
V ideo BIOS Cacheable Enabled Enabled
Sys tem BIOS Cac heable Enabled Enabled
Memory Hole A t 15Mb A ddr Dis abled Dis abled
A GP A perture Siz e 64M 64M
CPU Fan On/Of f On Suspend On On
OnChip USB Dis abled Dis abled
CPU Warning Temperature Dis abled 70C / 158F