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S1571 D1181-001 http://www.tyan.com
permitting caching of the video BIOS ROM at C0000h to C7FFFh.
Note
that any program which tries to write to this area may cause a
system error.
Inserts a timing delay between the CAS and RAS strobe signals, used
when DRAM is refreshed, read from, or written to.
s
Fast RAS# to CAS# Delay
Select the time in HCLKs that the DRAM controller waits to close a
DRAM page after the CPU becomes idle.
When Enabled, the chipset keeps the page open until a page/row miss.
When Disabled, the chipset uses additional data to keep the DRAM page
open when the host may be only temporarily absent.
Do not change these values unless you change the specifications of the
installed DRAM or the installed CPU.
You can select a combination of CAS latency and RAS-to-CAS delay
in HCLKs of 2/2 or 3/3. The board designer should set these values
based
on the installed DRAM. As above, do not change the values in
this field
unless you change the specifications of the installed
DRAM or the installed CPU.
The chipset can guess at a DRAM read address in order to reduce
read
latencies. A read request containing the data memory address
is issued
by the CPU, and received by the DRAM controller. If this
function is Enabled, the controller issues the read command just
before it has
finished decoding the data address.
If Enabled, results in better system performance by permitting caching
of the system BIOS ROM at F0000h-FFFFFh. Any program which
tries to write to this memory area may cause a system error.
If Enabled, this function results in better video performance by
s
DRAM Page Idle Timer
s
DRAM Enhanced Paging
s
Fast MA to RAS# Delay
s
SDRAM (CAS Lat/RAS-to-CAS)
s
SDRAM Speculative Read
s
System BIOS Cacheable
s
Video BIOS Cacheable
BIOS Configuration
