TTI CPX200, Руководство по обслуживанию

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The +2·45V reference line VREF+A is derived from reference diode D23 attenuated to about
188mV by divider R83, R82 at the reference input of analogue to digital converter IC12, yielding a
sensitivity of about 92uV per digit.
The set current signal ISETA is taken from the VR4 wiper on the front panel board via PJ8 pin 2
and on to the ADC as IPROGA, via adjustable attenuating chain R92, VR3, R93, for display of the
preset current level.
The voltage control signal VSETA is derived from the wipers of the coarse and fine voltage
controls VR1 and VR2 on the front panel board via PJ8 pin 3 and on to the ADC as VPROGA via
adjustable attenuating chain R88, VR7, R89, for display of preset voltage level.
The OVP front panel preset potentiometer VR3 is fed from the reference voltage defined by zener
D4. The OVP set from VR3 wiper, OVPSETA, is fed via PJ8 pin 4 and on to the ADC input via
divider R90, R91 for display of preset over voltage trip level.
Actual output volts are fed from the main board, via PJ4 pin 9 (+VESENSEA) and PJ4 pin 10 (–
VESENSEA), to attenuating chain R78, VR8 and R80 and on to the ADC.
The voltage across the current sense resistor, attenuated by R18 and VR1 (main board) is fed via
PJ4 pin 1 (O/P CURRENT SENSE +A) and PJ4 pin 2 (O/P CURRENT SENSE –A) to the ADC.
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