1
1
2
2
3
3
4
4
D
D
C
C
B
B
A
A
Date:
Page
31
of
32
Number:
Title:
TEF1001 - Clock Overview
01
Rev.
A4
Copyright:
Trenz Electronic GmbH
CLOCKS OVERVIEW.SchDoc
Filename:
2017-02-14
Default
TEF1001
PCIe 8x
SiT8208AI
SI5338A
25 MHz
1V8
VDDO_0
VDDO_1
VDDO_2
VDDO_3
CLK_0
CLK_1
CLK_2
CLK_3
BANK_14
(VCCO= 1V8 )
BANK_14
(VCCO= 1V8 )
BANK_14
(VCCO= 1V8 )
MGT_BANK_115
MGTREFCLK0_115
MRCC
MRCC
SRCC
1V8
1V8
1V8
MGT_BANK_115
MGTREFCLK1_115
CONNECTOR
MGT_BANK_116
MGTREFCLK0_116
MGT_BANK_116
MGTREFCLK1_116
FMC
CONNECTOR
CLK0
CLK1
CLK2
MGTCLK
PCIE_CLK
GBTCLK0_M2C
GBTCLK1_M2C
BANK_15
(VCCO= VADJ)
SRCC
SRCC
BANK_13
SRCC
SRCC
CLK0_M2C
CLK1_M2C
BANK_15
(VCCO= VADJ)
CLK2_BIDIR
CLK3_BIDIR
BANK_13
(VCCO= VADJ)
(VCCO= VADJ)
MRCC
DDR3_CLK
BANK_33
(VCCO= 1V5 )
DSC1123
SYSTEM CLOCK
TERMINATION
200 MHz
SOCKET
DDR3
(VDD= 1V5 )
DDR3_CLK0
DDR3_CLK1
