Toshiba TMPM3V4, Руководство пользователя

Страница: 219 / 544

11.3.10 UARTxIFLS (UART Interrupt FIFO Level Selection Register)
31 30 29 28 27 26 25 24
Bit symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit symbol - - RXIFLSEL TXIFLSEL
After reset 0 0 0 0 0 0 0 0
Bit Bit symbol Type Function
31-6 − R Read as an undefined value.
5-3 RXIFLSEL[2:0] R/W Selects the reception interrupt FIFO level
000: The Receive FIFO ≥ full of 1/8
001: The receive FIFO ≥ full of 1/4
010: The receive FIFO ≥ full of 1/2
011: The receive FIFO ≥ full of 3/4
100: The receive FIFO ≥ full of 7/8
Other than the above settings: Reserved
Selects the receive FIFO interrupt level. The FIFO level is not a trigger of interrupts. Interrupts is gener-
ated when the transition is made through the specified FIFO level. For example, if the FIFO level is set to
full of 1/8 (4 bytes), when the 4th byte data is stored in the receive FIFO, an interrupt occurs (after a
STOP bit is received).
2-0 TXIFLSEL[2:0] R/W Selects the transmission interrupt FIFO level
000: The transmit FIFO ≤ full of 1/8
001: The transmit FIFO ≤ full of 1/4
010: The transmit FIFO ≤ full of 1/2
011: The transmit FIFO ≤ full of 3/4
100: The transmit FIFO ≤ full of 7/8
Other than the above settings: Reserved
Selects the transmit FIFO interrupt level. Interrupts are not generated at reaching to the specified interrupt lev-
el. They are generated when the transition is made through the specified interrupt level. For example, if
the FIFO level is set to full of 1/8 (4 bytes), when the 5th data is read from the transmit FIFO (when transmis-
sion of a STOP bit is started), when data in the FIFO increases to 4bytes, an interrupt occurs.
TMPM3V6/M3V4
Page 197
2019-02-06