Toshiba TMPM3V4, Руководство пользователя

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11.3.2 UARTxDR (Data Register)
31 30 29 28 27 26 25 24
Bit symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
Bit symbol - - - - - - - -
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
Bit symbol - - - - OE BE PE FE
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Bit symbol DATA
After reset 0 0 0 0 0 0 0 0
Bit Bit symbol Type Function
31-12 − R Read as "0".
11 OE R Overrun error
0: No error
1: Error
If the FIFO has been full when receiving data, this bit is set to "1".
When the FIFO has empty space and new data can be written to FIFO, this bit is cleared to "0".
10 BE R Break error
0: No error
1: Error
If break condition (the UTxRXD input is kept to "Low" longer than accumulated time of a start bit, data bit, par-
ity bit, and stop bit) is detected, this bit is set to "1".
If the FIFO is enabled, this error is stored at the top of the FIFO. If a break error occurs, "0" is stored in
the FIFO as data.
Next data reception is enabled after the UTxRXD input is "1" (marking state) and the start bit is received.
9 PE R Parity error
0: No error
1: Error
When this bit is set to "1", this indicates that a received data parity does not match the parity programmed
with UARTxLCR_H<EPS> and <SPS>.
If the FIFO is enabled, this error is stored at the top of FIFO.
8 FE R Framing error
0: No error
1: Error
When this bit is set to "1", this indicates that received data does not include a valid stop bit. (A valid stop
bit length is "1".)
If the FIFO is enabled, this error is stored at the top of FIFO.
7-0 DATA[7:0] R/W [Read]
Receive data
[Write]
Transmit data
Note: Error status can be identified by reading UARTxRSR as well.
TMPM3V6/M3V4
11. Universal Asynchronous Receiver-Transmitter Circuit (UART)
11.3 Registers
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2019-02-06