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Verdin Carrier Board Design Guide

Preliminary

– Subject to Change

Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l +41 41 500 48 00 l

www.toradex.com

[email protected]

Page | 56

Verdin
Pin

Verdin
Signal Name

I/O

Type

Power
Rail

Description

206

GPIO_1

I/O

CMOS

1.8V

General purpose GPIO

208

GPIO_2

I/O

CMOS

1.8V

General purpose GPIO

210

GPIO_3

I/O

CMOS

1.8V

General purpose GPIO

212

GPIO_4

I/O

CMOS

1.8V

General purpose GPIO

216

GPIO_5_CSI

I/O

CMOS

1.8V

Reserved general-purpose IO for MIPI CSI interface

218

GPIO_6_CSI

I/O

CMOS

1.8V

Reserved general-purpose IO for MIPI CSI interface

220

GPIO_7_CSI

I/O

CMOS

1.8V

Reserved general-purpose IO for MIPI CSI interface

222

GPIO_8_CSI

I/O

CMOS

1.8V

Reserved general-purpose IO for MIPI CSI interface

GPIO_9_DSI

I/O

CMOS

1.8V

Reserved general-purpose IO for MIPI DSI interface

GPIO_10_DSI

I/O

CMOS

1.8V

Reserved general-purpose IO for MIPI DSI interface

Table 33: Dedicated GPIO Signals

2.18.2

Unused GPIO Termination

The GPIO signals do not need to be terminated if they are not in use.

2.19

JTAG interface

The Verdin module specification features JTAG test interface signals on the module edge

connector. The JTAG interface can be useful for advanced debugging of the main and real-time (if

available) operating system.

2.19.1

JTAG Signals

The JTAG signals have normally an IO voltage level of 1.8V. However, there could be modules

with a different JTAG voltage level. Therefore, the JTAG interface has a voltage reference output

which represents the IO voltage of the module. This rail should be used for the JTAG adapter as

reference voltage.

The JTAG_1_TRST# signal is an optional signal that allows the test adapter to reset the devises on

the JTAG interface. It depends on the module, whether the TRST signal is available and whether it

also resets further peripherals on the module.

Verdin
Pin

Verdin
Signal Name

I/O

Type

Power Rail

Description

JTAG_1_TDI

CMOS

JTAG_1_VREF

Test Data In

JTAG_1_TDO

CMOS

JTAG_1_VREF

Test Data Out

JTAG_1_TCK

CMOS

JTAG_1_VREF

Test Clock

JTAG_1_TMS

CMOS

JTAG_1_VREF

Test Mode Select

JTAG_1_TRST#

CMOS

JTAG_1_VREF

Test Reset (optional)

JTAG_1_VREF

CMOS

1.8V*

Reference output voltage for JTAG adapter

Table 34: JTAG Signals

2.19.2

Reference Schematics

Figure 45: JTAG Example Schematic

FTSH-105-01-L-DV-K

X56

JTAG_1_TDI

JTAG_1_TRST#

JTAG_1_TDO

JTAG_1_VREF

JTAG_1_TCK

JTAG_1_TMS

X1A

2309409-2

JTAG_1_TDI

JTAG_1_TRST#

JTAG_1_TDO

JTAG_1_TCK

JTAG_1_TMS

JTAG_1_TMS
JTAG_1_TCK
JTAG_1_TDO
JTAG_1_TDI
JTAG_1_TRST#

JTAG_1_VREF

GND

JTAG Header

JTAG[0..4]

Содержание Verdin

Страница 1: ...Verdin Computer Module Carrier Board Design Guide...

Страница 2: ...se Preliminary Version October 16 2020 V0 91 Correct position of standoff holes in carrier board land pattern drawing Figure 92 Remove additional notches from the drawings of the module October 28 202...

Страница 3: ...ent Ethernet Port 21 2 3 2 Reduced Gigabit Media Independent Interface Ethernet Port 24 2 4 USB 25 2 4 1 USB Signals 26 2 4 2 Reference Schematics 27 2 4 3 Unused USB Signal Termination 32 2 5 HDMI DV...

Страница 4: ...put Signal Termination 55 2 18 GPIO 55 2 18 1 GPIO Signals 55 2 18 2 Unused GPIO Termination 56 2 19 JTAG interface 56 2 19 1 JTAG Signals 56 2 19 2 Reference Schematics 56 2 19 3 Unused JTAG Signal T...

Страница 5: ...sues 83 3 5 5 Backfeeding Prevention 86 4 Mechanical and Thermal Consideration 95 4 1 Module Connector and Stacking Height 95 4 2 Fixation of the Module 96 4 3 Thermal Solution 96 4 4 Module Dimension...

Страница 6: ...additional information on the routing of these interfaces 1 2 Additional Documents 1 2 1 Layout Design Guide This document contains layout requirement specifications for high speed signals and helps t...

Страница 7: ...izes CEC Consumer Electronic Control HDMI feature that allows to control CEC compatible devices CPU Central Processor Unit CSI Camera Serial Interface DAC Digital to Analog Converter DDC Display Data...

Страница 8: ...ernet PHY and cable connector MDIO Management Data Input Output an interface that is used for controlling the Ethernet PHY The bus consists of the MDC clock and the MDIO bidirectional data signal MDIX...

Страница 9: ...tion card for GSM phones SMBus System Management Bus SMB two wire bus based on the I2 C specifications used specially in x86 design for system management SoC System on a Chip IC which integrates the m...

Страница 10: ...nterfaces and some examples of Module specific interfaces 1x Gigabit Ethernet 1x RGMII 1x LVDS 1x USB 2 0 OTG 1x USB 2 0 Host 1x I2C 1x SPI 3x UART RX TX only 1x PWM 10x GPIO 1x SDIO 1x USB SuperSpeed...

Страница 11: ...rier board combination may disable any all functionalities or even possibly damage the SoM and or the carrier board Using or relying on functionalities provided on Module specific pins or interfaces i...

Страница 12: ...s during the design of Verdin SoMs these instances are prioritized according to the availability of the interface they belong to For example there are up to four I2 C instances in the Verdin specifica...

Страница 13: ...ional PCI Express lanes It should be noted that Module specific interfaces will be kept common across modules that share such interfaces whenever possible For example if both module A and module B hav...

Страница 14: ...zerland l 41 41 500 48 00 l www toradex com l info toradex com Page 14 Figure 2 Pin numbering schema on the bottom side of the module bottom view Figure 3 Pin numbering schema on the module connector...

Страница 15: ...ces as Module specific interfaces Please consult the datasheets of such modules to determine if lane reversal is applicable and supported 2 2 2 Reference Schematics The PCIe schematic differs dependin...

Страница 16: ...uch as Ethernet cards can use this signal to wake up the module from the suspend state The WAKE signal of the PCIe card slot is an open drain type Therefore no level shifter is required if the signal...

Страница 17: ...erfaces the PCIe and USB As most of the Mini PCIe Cards use only one of its interfaces for an embedded carrier board which is developed for a restricted set of compatible cards it might be enough to i...

Страница 18: ...E signal of the Mini PCIe Cards slot is an open drain type Therefore no level shifter is required if the signal is pulled up to 1 8V on the carrier board and not to 3 3V The R UIM interface of the Min...

Страница 19: ...R3 I2C1_SDA I2C1_SCL GND PCIE1_WDISABLE V3 3_PCIE V1 5 LED1 LED2 LED3 150R R6 150R R7 150R R8 V3 3_SW PCIE1_WWLAN PCIE1_WLAN PCIE1_WPAN USBH_D_P USBH_D_N USBH 0 1 V3 3_SW V3 3_SW V3 3_SW PCIE1_RX_N P...

Страница 20: ...ET_MOCI WAKE1_MICO I210 PE_RX_P 24 PE_CLK_P 26 PE_CLK_N 25 JTAG_TCK 19 JTAG_TDO 4 JTAG_TMS 18 JTAG_TDI 29 SMB_DATA 36 SMB_CLK 34 PE_TX_P 21 PE_TX_N 20 SDP0 63 XTAL_1 46 MDI_0_P 58 PE_RX_N 23 PE_RST 17...

Страница 21: ...Reserved interface The RGMII requires a PHY to be placed on the carrier board and allows using multiple types of media for the physical link layer 2 3 1 Media Dependent Ethernet Port The Verdin featur...

Страница 22: ...he magnetics Do not connect the center taps together The Ethernet connector with integrated magnetics provides a certain amount of protection against ESD If a higher level is required optional ESD pro...

Страница 23: ...m Verdin Module Magnetics Ethernet Jack RJ 45 LINK LED ACT LED 2mm 100nF 16V C6 100nF 16V C7 100nF 16V C8 150R R6 150R R5 ETH1_MDI0_N ETH1_MDI1_P ETH1_MDI1_N ETH1_MDI2_P ETH1_MDI2_N ETH1_MDI3_P ETH1_M...

Страница 24: ...Ethernet PHY In these cases special care must be taken that the address of the carrier board PHY does not conflict with the on module PHY address 2 3 2 1 RGMII Signals Verdin Pin Verdin Signal Name I...

Страница 25: ..._2_MDI3_N ETH_2_MDI3_P ETH_2_ACT ETH_2_LINK BAT54XV2T5G D17 BAT54XV2T5G D18 AVDDH 1 AVDDL 4 AVDDL 9 AVDDH 12 NC 13 NC 14 DVDDH 16 DVDDL 18 DVDDL 23 DVDDL 26 VSS 29 DVDDL 30 DVDDH 34 DVDDL 39 DVDDH 40...

Страница 26: ...ansfer Mode Naming Schemes The first generation Gen 1 uses 8b 10b encoding while the second generation Gen 2 uses the more efficient 128b 132b encoding This is the reason why the second generation can...

Страница 27: ...ving pins should be called RX Please read carefully the datasheet of the USB device device down in order to ensure RX and TX are not confused 2 4 2 1 USB 2 0 OTG Schematic Example If the USB signals a...

Страница 28: ...OTG ID signal which can be used with the Verdin module If the port has negotiated being source for the power Downstream Facing Port DFP the VBUS need to be provided The TUSB321 can be strapped to ann...

Страница 29: ...GND 100nF 16V C11 GND GND 10uF 10V C13 ESD9101P2T5G D1 GND 12R 100MHz 1 2 3 4 L2 USB_1_CC1 USB_1_CC2 100uF 10V C17 100uF 10V C14 R66 100K V1 8_SW 10K R18 10K R21 28 7K R17 GND GND GND TP15 TP16 TP17 T...

Страница 30: ...Speed RX lane TX from the device need to be placed on the carrier board As the capacitors for the TX lane are located on the Verdin module no additional capacitors are required nor permitted on the TX...

Страница 31: ...TREAM 4 IC11 USB5744T I 2G USB_2_SSRX_P USB_2_SSRX_N USB_2_SSTX_P USB_2_SSTX_N USB_2_D_P USB_2_D_N USBH_RESET GND GND GND USBH_RBIAS USBH_TEST GND USBH_CFG_BC_EN 4 2 OSC1B QC5A25 0000F10B22R GND 1 3 O...

Страница 32: ...lave 159 USB_1_VBUS Leave NC if not used 155 USB_1_EN Leave NC if not used 157 USB_1_OC Add pull up resistor or disable the over current function in software 183 USB_2_D_P Leave NC if not used 181 USB...

Страница 33: ...Verdin Signal Name I O Type Power Rail Description 69 HDMI_1_TXC_P O TDMS HDMI DVI differential clock positive 67 HDMI_1_TXC_N O TDMS HDMI DVI differential clock negative 75 HDMI_1_TXD0_P O TDMS HDMI...

Страница 34: ..._TXC_P 69 HDMI_1_TXD1_N 79 HDMI_1_TXD0_P 75 HDMI_1_TXC_N 67 HDMI_1_CEC 63 HDMI_1_HPD 61 I2C_3_HDMI_SCL 59 I2C_3_HDMI_SDA 57 HDMI_1_TXD1_P 81 HDMI_1_TXD2_N 85 HDMI_1_TXD2_P 87 X1D 2309409 2 V1 8_SW GND...

Страница 35: ...disable the I2C function in software 59 I2C_3_HDMI_SCL Add pull up resistor or disable the I2C function in software Table 13 Unused HDMI DVI signal termination 2 6 Display Serial Interface MIPI DSI Th...

Страница 36: ...I2 C a PWM and two GPIOs for the DSI interface These signals are intended to be used for controlling an attached display as well as DSI bridges Some DSI bridges can embed also sound in the interface e...

Страница 37: ...Hz 800mA L11 220R 100MHz 800mA L10 220R 100MHz 800mA L5 220R 100MHz 800mA L9 220R 100MHz 800mA L6 220R 100MHz 800mA L7 220R 100MHz 800mA L8 10uF 6 3V C35 100nF 16V C36 GND 10uF 6 3V C22 100nF 16V C23...

Страница 38: ...12 RSVD 13 RSVD1 34 RSVD2 1 SCL 15 SDA 16 IRQ 33 REFCLK 17 EN 2 ADDR 64 VCORE 31 IC5 SN65DSI84TPAPRQ1 GND 100nF 16V C35 GND 10nF 16V C36 GND 100nF 16V C33 GND 10nF 16V C34 GND GND R28 10K GND GND DIFF...

Страница 39: ...CP D2 I2S_LRCLK D4 I2S_BCLK D5 SD I2S_OSCLK D6 I2S_DATA D7 DPI_D13 D9 DPI_D14 D10 VDD_DSI12 E1 I2C_ADR_SEL E2 VSS E4 TEST3 E5 VPGM0 E6 DPI_D10 E7 DPI_D16 E9 DPI_D15 E10 IC5 DSI_1_D0_N DSI_1_D0_P DSI_1...

Страница 40: ...ed to be used as DDC 54 I2C_2_DSI_SDA I O 58 PWM_3_DSI I O CMOS 1 8V Dedicated PWM for the display backlight brightness control could also be used as general purpose IO 8 GPIO_9_DSI I O CMOS 1 8V Dedi...

Страница 41: ...ust be taken at the pin numbering Even though the adapter and the carrier board connector are identical the footprint with the pin numbering must be different Figure 34 Carrier board dimensions for MI...

Страница 42: ...ware 53 I2C_2_DSI_SDA Add pull up resistor or disable the I2C function in software 19 PWM_3_DSI Leave NC if not used 17 GPIO_9_DSI Leave NC if not used 21 GPIO_10_DSI Leave NC if not used Table 17 Unu...

Страница 43: ...e chokes are optional The protection diodes are only required if the cables are accessible and or the display does not have enough protection The chokes can reduce EMI if the LVDS cables are longer Fi...

Страница 44: ...fault Speed High Speed 50 MHz 25 MB s 3 3V High Speed SDR12 25 MHz 12 5 MB s 1 8V UHS I SDR25 50 MHz 25 MB s 1 8V DDR50 50 MHz 50 MB s 1 8V SDR50 100 MHz 50 MB s 1 8V SDR104 208 MHz 104 MB s 1 8V Tabl...

Страница 45: ...ation All unused SD interface signals can be left unconnected If the SD MMC SDIO ports is unused the signal could be used as GPIO Check the datasheet of the Verdin module whether there are any restric...

Страница 46: ...n be configured as GPIO 2 10 UART There are four UART ports available in the Verdin module standard UART_1 and UART_2 are general purpose interfaces The RX and TX signals of these interfaces are in th...

Страница 47: ...eral purpose UART_2 143 UART_2_CTS I CMOS 1 8V Clear to Send of general purpose UART_2 151 UART_4_RXD I CMOS 1 8V Received Data for real time core debug UART_4 153 UART_4_TXD O CMOS 1 8V Transmitted D...

Страница 48: ...it is recommended to keep the inverter circuit in in the RTS signal to maintain compatibility with different modules and drivers provided by Toradex For some applications it is desirable that the UART...

Страница 49: ...e these different behaviors Make sure that the relevant Verdin module and the peripheral devices are set to the same SPI mode SPI Mode Clock Polarity Clock Phase Description 0 0 0 Clock has positive p...

Страница 50: ...unication for much higher speed than regular SPI Regular SPI uses individual single data lines for transferring and receiving data full duplex Even though QSPI is very often used as a short form for Q...

Страница 51: ...ypes of connectors used for the CAN interface The reference schematic below uses single row pin header as connector Since this is not an official standard some devices might have a different connector...

Страница 52: ...nteed to be pin compatible with other Verdin modules The maximum output frequency and the possible duty cycle steps vary between the different Verdin modules Please carefully read the datasheets of Ve...

Страница 53: ...ronization signal is used for identifying whether the data belongs to the right or left channel and marks the start of each word In the I2 S standard the sync and clock signal can be generated either...

Страница 54: ...Pink SJ1 3535NG PI X22 22R RA13D 22R RA14A 22R RA14B 22R RA14C 22R RA14D I2S_1 0 4 I2S_1_BCLK 30 I2S_1_SYNC 32 I2S_1_D_OUT 34 I2S_1_D_IN 36 I2S_1_MCLK 38 I2S_2_BCLK 42 I2S_2_SYNC 44 I2S_2_D_OUT 46 I2...

Страница 55: ...eries resistors should be placed close to the clock output of the module Start with a value of 22 Try to increase this value until the corresponding interface fails due to the signal quality of the cl...

Страница 56: ...l for advanced debugging of the main and real time if available operating system 2 19 1 JTAG Signals The JTAG signals have normally an IO voltage level of 1 8V However there could be modules with a di...

Страница 57: ...ype Power Rail Description 246 CTRL_RECOVERY_MICO I OD 1 8V Recovery mode strapping input Pull up resistor on module additional pull up on carrier board not allowed 165 USB_1_D_P I O USB USB interface...

Страница 58: ...l Switzerland l 41 41 500 48 00 l www toradex com l info toradex com Page 58 2 20 3 Unused Recovery Signal Termination The CTRL_RECOVERY_MICO can be left unconnected if the recovery feature is not nee...

Страница 59: ...Common signal and power ground 249 VCC_BACKUP I PWR 3 0V RTC supply can be left unconnected if internal RTC is not used 214 PWR_1V8_MOCI O PWR 1 8V 250mA output for carrier board peripherals Table 36...

Страница 60: ...VCC_BACKUP may be available for keeping the RTC running The CTRL_PWR_EN_MOCI and CTRL_SLEEP_MOCI are both low in order to make sure no peripheral rails on the carrier board are enabled CTRL_RESET_MOCI...

Страница 61: ...operating system this will start a software shut down or opens a menu which lets the customer decide what to do Pressing the power button longer than 5 seconds will shut the system down immediately wi...

Страница 62: ...CTRL_FORCE_OFF_MOCI for the first 400ms after VCC has been applied After the early module rails are ramped up the Verdin module outputs the PWR_1V8_MOCI output rail and releases the CTRL_PWR_EN_MOCI T...

Страница 63: ...ce The reset cycle can be initiated by a falling edge on the CTRL_RESET_MICO some modules add some debouncing time or by software In the preferred reset mode cold reset first the SoC reset and the CTR...

Страница 64: ...te starts when the CTRL_RESET_MICO is released and the minimum reset time has elapsed The actual reset time depends on the module The rails are turned back on in the same order as during a regular mod...

Страница 65: ...a low level at the CTRL_SLEEP_MOCI signal This signal is used by the carrier board for turning off any rails that are not required in the sleep mode It depends on the carrier board design which rails...

Страница 66: ...AKE1_MICO is the preferred wake source for keeping a design compatible between different Verdin modules The module re enables the voltage rails and sets the CTRL_SLEEP_MOCI signal high This enables th...

Страница 67: ...es or disconnecting services After all processes are stopped the last task of the operating system is to request a shut down from the PMIC The PMIC is first asserting the SoC reset as well as the CTRL...

Страница 68: ...s by saving temporary data flushing buffers closing files or disconnecting services On the other hand with force OFF the system can be shut down independently of the state of the operating system or o...

Страница 69: ...er than 5 seconds some modules will directly initiate a force OFF sequence Some modules will ignore a long press to the power button if the CTRL_PWR_BTN_MICO was not going high after detecting the pow...

Страница 70: ...is removed from the module The only rail that is still optionally supplied to the module is the VCC_BACKUP rail for the on module real time clock The carrier board should avoid of having any signal dr...

Страница 71: ...l IC which handles the switching of the main VCC for the module This approach makes use of the CTRL_FORCE_OFF_MOCI signal which switches off VCC after the module has been successfully shutdown 3 4 1 1...

Страница 72: ...C rail If the module is running a long pressing of the power button 5s is generating an emergency power shutdown of the system The power button control IC is forwarding the long press event to the CTR...

Страница 73: ...over current protection circuit In such cases tweak the soft start functions of the switches and regulators if available For designing the power supply on the carrier board a current consumption budge...

Страница 74: ...2 47uF 10V C73 GND GND GND GND 100nF 50V C64 5 0V Iout max 8A GND 10uF 50V C68 10uF 50V C69 GND GND V7 24 GND V5_STB 5V_PGOOD f sw 400KHz Tss 3 3mS GND DCDC1_SS 3 3uH 10A L10 DCDC2_LX 4 7uF 10V C65 GN...

Страница 75: ...er power source from 3 135V to 5 5V e g simple barrel connector power supply The 5V from the USB is directly connected to the VCC input voltage of the module No further buck regulator is needed The mo...

Страница 76: ...utton CTRL_RESET_MICO is not implemented in such a power scheme it is still possible to do software initiated reset cycles Without implementing a power button CTRL_PWR_BTN_MICO the only option for exi...

Страница 77: ...be used up with Verdin modules While this represents only a very small portion of total battery capacity it also helps to prevent battery deep discharge events from happening POWER ON OFF BUTTON Opti...

Страница 78: ...uired to be provided to the module The system voltage can range from 3 135V to 4 4V which makes the creation of a 3 3V 5 rail challenging A better approach is to run peripherals from 1 8V and reducing...

Страница 79: ...onal and irregular flow of current mainly over the signal path It can happen if interfaces are crossing different power domains Backfeeding can happen between circuit blocks powered by or switched by...

Страница 80: ...s can basically be ignored There is a small current flowing from the peripheral output to the input buffer of the SoC This is not backfeeding This is a regular signal current Figure 65 SoC input pin w...

Страница 81: ...ffset Even if the module and carrier board are turned off the TMDS signals can be lifted to 3 3V by the monitor If an improper HDMI circuit is used this can cause backfeeding The DDC and the hotplug d...

Страница 82: ...specified by a similar formula 0 3 The 0 3V in this formula is dictated by the ESD protection diode According to the device specifications the input voltage always needs to be small enough for not ha...

Страница 83: ...r delivery block diagram can help to identify different power domains A power domain is a group of devices or peripherals which are always in the same power state Figure 69 shows a simple example of a...

Страница 84: ...ernal peripherals and observe the residual voltage If the voltage drops the peripheral signals are likely a source of backfeeding If you measure residual voltage in one power domain all the input sign...

Страница 85: ...other method for estimating the number of backfeeding pins By adding a load resistor to the IO rail and observing the residual voltage changes the total internal resistance of the backfeeding can be e...

Страница 86: ...about three times smaller than a single signal pin This means there are probably a total of three similar signal pins that are backfeeding to this IO rail 3 5 5 Backfeeding Prevention There are multip...

Страница 87: ...peripherals on the same Domain 3 5 5 2 Avoid Driving Outputs High Backfeeding can be prevented by ensuring the output pin is not driven high while the IO rail of the input side is powered off This is...

Страница 88: ...the USB data signals Therefore no further backfeeding prevention is required for these signals on the carrier board Whenever you are selecting peripheral devices it is advised to check whether the in...

Страница 89: ...it is recommended to use this PWR_1V8_MOCI for open drain pull up resistors Figure 77 Correct pull up rail for open drain signals 3 5 5 6 Simple FET Circuit for Open Drain Signals Sometimes it is imp...

Страница 90: ...xternal resistor The advantage of the internal resistor is that it is using the correct IO rail The biggest drawback of this solution is that the low level of the signal is increased Therefore using a...

Страница 91: ...of this document carefully for understanding whether coupling capacitors are required on the carrier board or not Figure 81 Capacitive coupled signals 3 5 5 9 Non Backfeeding Buffer Placing an additi...

Страница 92: ...3 5 5 11 Tristate Buffer Tristate buffers that feature an output enable control signal can be a solution For example RS232 transceivers often feature an output enable signal The biggest challenge wit...

Страница 93: ...ain signals such as the I2 C bus the FXMA2102L8X from ON Semiconductor prevents backfeeding Figure 85 Level shifter for preventing backfeeding 3 5 5 13 Galvanic Isolation Galvanic isolations in the si...

Страница 94: ...g the power on reset or an incorrect device configuration strapped a solution might be adding an extra load to the affected rail Turning this load on only during the power up sequence is advisable for...

Страница 95: ...the SODIMM connector there is an area which allows for higher components such as decoupling capacitors or series resistors to be placed The maximum height in this area is listed in the column Compone...

Страница 96: ...odule a connector with a larger stacking height is recommended 4 2 Fixation of the Module The SODIMM DDR4 connector comes with an integrated clip mechanism for a fast secure and convenient fixation of...

Страница 97: ...connected Figure 91 Module dimension bottom side mm 4 5 Connector and Standoff Land Pattern Requirements The required land pattern depends on the need for additional standoffs The standoffs are optio...

Страница 98: ...re 92 Carrier Board Land Pattern mm 4 6 Carrier Board Space Requirements The required PCB area for the module depends on the module fixing method and the cooling solution 0 30 3 00 1 60 1 10 68 80 1 0...

Страница 99: ...GND 29 DSI_1_D2_N Differential Pair Output Reserved 31 DSI_1_D2_P Differential Pair Output Reserved 33 GND 35 DSI_1_CLK_N Differential Pair Output Reserved 37 DSI_1_CLK_P Differential Pair Output Rese...

Страница 100: ...I_1_D1_N Differential Pair Input Reserved 121 GND 123 CSI_1_D0_P Differential Pair Bidirectional Reserved 125 CSI_1_D0_N Differential Pair Bidirectional Reserved 127 GND 129 UART UART_1_RXD Input 1 8V...

Страница 101: ...t 1 8V Reserved 209 GND 211 ETH_2_RGMII_TX_CTL Output 1 8V Reserved 213 ETH_2_RGMII_TXC Output 1 8V Reserved 215 ETH_2_RGMII_TXD_3 Output 1 8V Reserved 217 ETH_2_RGMII_TXD_2 Output 1 8V Reserved 219 E...

Страница 102: ...nary Subject to Change Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l 41 41 500 48 00 l www toradex com l info toradex com Page 102 257 VCC Power Input 3 135 5 5V Always Compatible 259 VCC...

Страница 103: ...Bidirectional 1 8V Reserved 34 I2S_1_D_OUT Output 1 8V Reserved 36 I2S_1_D_IN Input 1 8V Reserved 38 I2S_1_MCLK Output 1 8V Reserved 40 GND 42 I2S_2_BCLK Bidirectional 1 8V Reserved 44 I2S_2_SYNC Bidi...

Страница 104: ...20 MSP_15 Differential Pair Single Ended Module specific 122 GND 124 MSP_16 Differential Pair Single Ended Module specific 126 MSP_17 Differential Pair Single Ended Module specific 128 MSP_18 GND Low...

Страница 105: ...ectional 1 8V Always Compatible 208 GPIO_2 Bidirectional 1 8V Always Compatible 210 GPIO_3 Bidirectional 1 8V Always Compatible 212 GPIO_4 Bidirectional 1 8V Always Compatible 214 PWR_1V8_MOCI 1 8V Ou...

Страница 106: ...Change Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l 41 41 500 48 00 l www toradex com l info toradex com Page 106 258 CTRL_RESET_MOCI Open Drain Output 3 3V Tolerant Always Compatible 260...

Страница 107: ..._D3_N 23 24 CAN_2_TX DSI_1_D3_P 25 26 CAN_2_RX GND 27 28 GND I2S DSI_1_D2_N 29 30 I2S_1_BCLK DSI_1_D2_P 31 32 I2S_1_SYNC GND 33 34 I2S_1_D_OUT DSI_1_CLK_N 35 36 I2S_1_D_IN DSI_1_CLK_P 37 38 I2S_1_MCLK...

Страница 108: ...112 MSP_11 CSI_1_CLK_N 113 114 MSP_12 GND 115 116 MSP_13 CSI_1_D1_P 117 118 MSP_14 CSI_1_D1_N 119 120 MSP_15 GND 121 122 GND CSI_1_D0_P 123 124 MSP_16 CSI_1_D0_N 125 126 MSP_17 GND 127 128 MSP_18 UART...

Страница 109: ...204 GND GPIO ETH_2_RGMII_RXD_2 205 206 GPIO_1 ETH_2_RGMII_RXD_3 207 208 GPIO_2 GND 209 210 GPIO_3 ETH_2_RGMII_TX_CTL 211 212 GPIO_4 ETH_2_RGMII_TXC 213 214 PWR_1V8_MOCI ETH_2_RGMII_TXD_3 215 216 GPIO...

Страница 110: ...Design Guide Preliminary Subject to Change Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l 41 41 500 48 00 l www toradex com l info toradex com Page 110 VCC 257 258 CTRL_RESET_MOCI VCC 259...

Страница 111: ...nformation and content in this document are provided as is with no warranties of any kind and are for informational purposes only Data and information have been carefully checked and are believed to b...

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