TMC TI5VG, Руководство пользователя

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Chapter 6 BIOS Configuration
TI5VG Pentium VP3 ATX Motherboard User’s Manual 41
6.5 Chipset Features Setup
This Setup menu controls the configuration of the motherboard chipset.
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
Bank 0/1 DRAM Timing : Normal OnChip USB : Disabled
Bank 2/3 DRAM Timing : Normal
Bank 4/5 DRAM Timing : Normal
SDRAM Cycle Length 2 CPU Warning Temperature : Disabled
SDRAM Bank Interleave 2 Bank Current CPU Temperature : 38
°
C/ 100
°
F
DRAM Read Pipeline : Enabled Current System Temperature : 0
°
C/ 32
°
F
Sustained 3T Write
:
Enabled Current CPUFAN1 Speed : 4927 RPM
Cache Rd+CPU Wt Pipeline
:
Enabled Current CPUFAN2 Speed : 4963 RPM
Read Around write
:
Enabled
Cache Timing
:
Fast
Video BIOS Cacheable
:
Enabled IN1 (V) : 0.25V
System BIOS Cacheable
:
Disabled IN2 (V) : 1.02V IN3(V) : 6.54V
Memory Hole At 15MB
:
Disabled IN4 (V) : 10.50V IN5 (V) : - 1.89V
AGP
:
Enabled IN6 (V)) : - 3.10V
Aperture Size
:
64M
AGP-2X Mode
:
Disabled
ESC : Quit
Ç È Æ Å
: Select Item
F1 : Help PU/PD/+/- : Modify
F5 : Old Values (Shift) F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
Bank DRAM Timing
These fields defines the speed of the DRAM memory onboard. The
options are
Normal , Medium , Fast , Turbo , 70ns and 60ns . By default,
this fields are set to Normal .
DRAM Cycle Length
This field sets the length of the SDRAM cycle. The options are 2 and 3 .
By default, this field is set to 2 .
DRAM Bank Interleave
This field sets the SDRAM banks in which the data is interleaved. The
options are
Disabled , 2 Bank and 4 Bank . By default, this field is set 2
Bank .
DRAM Read Pipeline
When enabled, this field supports pipelining of DRAM reads The default
setting is
Enabled
.
Sustained 3T Write
This field allows support for PBSRAM sustained 3T write. By default,
this field is set
Enabled .