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5.1.5

Reserved

The 96Boards specification calls for a 10K pull-up to 1.8V to be connected to pin 60 of the High Speed

Expansion Connector.

In C865 DEV KIT, a NC resistor is used in HS1 to connect pin60 of HS1 to 1.8V.

5.1.6

SD/SPI

The 96Boards specification calls for an SD interface or a SPI port to be part of the High Speed

Expansion Connector.

The C865 DEV KIT provides a full SD master with SDIO (CLK/CMD/D0~D3) from SM8250 SoC.

All signals are driven at 1.8V and 1.8V only.

5.1.7

Camera Clocks

The 96Boards specification calls for one or two programmable clock interfaces to be provided on the

High Speed Expansion Connector. These clocks may have a secondary function of being CSI0_MCLK

and CSI1_MCLK. If these clocks can’t be supported by the SoC than an alternative GPIO or No-

Connect is allowed by the specifications.

HS1 in C865 DEV KIT implements two CSI clocks, CLK0/CSI0_MCLK, GPIO_94 for CSI0 and

CLK3/CSI3_MCLK, GPIO_97 for CSI3. These signals are driven at 1.8V.

5.1.8

USB

The 96Boards specification calls for a USB data line interface to be present on the high-speed

expansion connector.

C865 DEV KIT implements this requirement. In HS1, USB HS DP/DM signals are routing from a

USB HUB.

5.2

Secondary High Speed Connector: HS2

PIN

C865 DEV KIT Signals

Note

PCIE_REFCLK_M

PCIE_REFCLK_P

PCIE_RX_M

PCIE_RX_P

Содержание TurboX C865 Dev Kit

Страница 1: ...1 TurboX C865 Dev Kit Hardware User Guide Rev A June 06 2020...

Страница 2: ...www thundercomm com 2 Revision history Revision Date Description 0 1 May 26 2020 Initial Release 1 0 June 06 2020 Delete box content description...

Страница 3: ...tart the board 12 2 1 Required equipment 12 2 2 OS startup process 12 3 TurboX C865 Dev Kit 14 3 1 System Block diagram 14 3 2 Processor 15 3 3 Memory 15 3 4 MicroSD 15 3 5 Wi Fi BT 16 3 6 Display Int...

Страница 4: ...ctionality 20 3 18 1 Ethernet Connector 20 3 18 2 Inertial Sensors 21 3 18 3 DIP Switch 21 3 18 4 Extra Low Speed Expansion Connector 22 3 18 5 Extra High Speed Expansion Connectors 22 4 Low speed Exp...

Страница 5: ...4 3 4 Other signals on Tertiary Low Speed Connector 34 5 High speed expansion connectors 36 5 1 Primary high speed expansion connector HS1 36 5 1 1 MIPI DSI 38 5 1 2 MIPI CSI 39 5 1 3 I2C 39 5 1 4 HS...

Страница 6: ...49 6 3 Power Sequencing 49 6 4 Power Measurements 49 6 4 1 DC In measurement 49 6 4 2 PMIC Power In measurement VPH_PWR measurement 49 7 Buttons and status LED s 51 7 1 Buttons 51 7 1 1 Volume up 51 7...

Страница 7: ...ndix 57 10 1 Navigation Mezzanine 57 10 1 1 Technical specifications 57 10 1 2 Board views 58 Top view 58 Bottom view 58 10 2 Machine Communication Mezzanine 59 10 2 1 Technical specifications 59 10 2...

Страница 8: ...sists of C865 Dev kit C865 SOM and Main IO board and accessories Navigation Mezzanine and Machine Communication Mezzanine The C865 Dev Kit is a 96Boards compliant community board based on the Qualcomm...

Страница 9: ...L MIPI DSI x 1 LS1 1 x 96boards 40 pin low speed connector UART x 2 SPI I2S PCM I2C x 2 GPIO x 12 DC powers LS2 1 x 96boards 40 pin low speed connector Speaker x 2 DMIC I F x 3 CAN I2S GPIOs PWM ADC I...

Страница 10: ...www thundercomm com 10 1 2 Board views C865 Main IO board 1 2 1 Top view 1 2 2 Back view...

Страница 11: ...finitions Component Description QUP Qualcomm Universal Peripheral The QUP engine provides a general purpose data path that supports multiple mini cores e g UART I2C and SPI CCI Camera Control Interfac...

Страница 12: ...nsole interface and ADB Fastboot commands USB to USB Type C cable For connecting the USB3 0 Type C port and flashing images Host PC For connecting the board and installing Fastboot 2 2 OS startup proc...

Страница 13: ...able USB port on the host PC NOTE Set the Bps Par Bits to 115200 8N1 5 Connect the power supply to power connector see section 1 2 1 14 6 Plug the power supply into a power outlet 7 Press and hold the...

Страница 14: ...www thundercomm com 14 3 TurboX C865 Dev Kit 3 1 System Block diagram Block diagram part 1 Block diagram part 2...

Страница 15: ...ncy 3 3 Memory The SM8250 uses a package on package PoP LPDDR5 RAM configuration and discrete UFS3 0 flash memory The LPDDR5 interface goes directly to the SM8250 built in LPDDR controller The maximum...

Страница 16: ...ntenna socket 26 for Wi Fi chain 0 and optionally BT and antenna socket 24 for Wi Fi chain1 are just backup solutions 3 6 Display Interface 3 6 1 HDMI The 96Boards specification calls for an HDMI port...

Страница 17: ...DSI HDMI Bridge When the signal of DIP switch is set to ON state DIP_HDMI_SWITCH is logic LOW 0 MIPI DSI signals will be routed to the High Speed Expansion connector 3 6 2 MIPI DSI C865 DEV KIT has 2...

Страница 18: ...ferent peripherals The board can work in one mode at a time NOTE There is a micro USB port section1 2 2 21 The micro B USB port is only for debug log output from the SM8250 debug UART to USB transform...

Страница 19: ...calls for the presence of two buttons a power on sleep button and a reset button C865 DEV KIT meets these requirements See Section 7 for details on C865 DEV KIT buttons 3 13 External Fan connection Th...

Страница 20: ...wer management IC PM8150L The fourth one is driven by the PM8250 via GPIO_10 Power indicator LED A Green LED 3 17 Expansion Connector The 96Boards specification calls for two expansion connectors a lo...

Страница 21: ...board MIC when set to OFF will enable DMIC1 on LS2 Switch 2 DIP_DEBUG_UART_SWITCH When set to ON position will enable on board debug UART when set to OFF will enable UART1 on LS1 Switch 3 CBL_PWR_N W...

Страница 22: ...G 2 Switch 3 BOOT_CONFIG 3 Switch 4 BOOT_CONFIG 0 3 18 4 Extra Low Speed Expansion Connector C865 DEV KIT has 3 extra low speed expansion connectors See Section 4 for detail 3 18 5Extra High Speed Exp...

Страница 23: ...S QUP13 5 UART0_TXD QUP13 7 UART0_RXD QUP13 9 UART0_RTS QUP13 11 UART1_TXD QUP12 13 UART1_RXD QUP12 15 I2C0_SCL QUP4 17 I2C0_SDA QUP4 19 I2C1_SCL QUP15 21 I2C1_SDA QUP15 23 GPIO A QUP A0 QUP1 25 GPIO...

Страница 24: ..._DI I2S_D0 24 GPIO B PCM0_MCLK 26 GPIO D QUP_A3 QUP1 28 GPIO F DISPLAYMIPI_ERR_ FG QUP15 30 GPIO H DISP_RST_N 33 GPIO J CAM0_PWDN 34 GPIO L CAM1_PWDN 36 DC12V 38 DC12V 40 GND 4 1 1 UART The 96Boards s...

Страница 25: ...DEV KIT implements this requirement Twelve GPIOs are routed from the SM8250 SoC The GPIOs are 1 8V voltage rail GPIO A QUP_A0 Connects to GPIO_4 of SM8250 SoC Can be configured to be an IRQ line GPIO...

Страница 26: ...ation of this signal should not drive it with any voltage the only allowed operation is to force it to GND to start the board from a sleep mode A board shutdown will occur when this signal is held to...

Страница 27: ...Dev Kit Signal Additional Info 1 GPIO_U CAM3_RST_N 3 DMIC_CLK1_LS2 5 DMIC_DATA1_LS2 7 GPIO_V I2S1_DATA2 ext codec CAM0_STROBE_N 9 DMIC_CLK2 11 DMIC_DATA2 13 GPIO_W I2S1_DATA3 ext codec CAM5_RST_N 15...

Страница 28: ...4 CAN_H 6 CAN_L 8 VREG_IO_1P8 10 GND 12 PM_GPIO A PM8150L GPIO6 14 PM_GPIO B PM8150L GPIO10 16 GPIO M QUP B0 QUP9 18 GPIO N QUP B1 QUP9 20 GPIO O QUP B2 QUP9 PWM 22 GPIO P QUP B3 QUP9 BOOT_CONFIG 0 2...

Страница 29: ...pment board 3 pairs of DMIC signals are routed to LS 4 2 2 Stereo speaker The speaker signals are routed from the 2 on board WSA8815 The signals are SPK0_P Class D speaker amplifier output SPK0_M Clas...

Страница 30: ...SDA2 Connects to CCI2 of SM8250 SoC Be configured to I2C SDA CCI_I2C_SCL2 Connects to CCI2 of SM8250 SoC Be configured to I2C SCL CCI_I2C_SDA3 Connects to CCI3 of SM8250 SoC Be configured to I2C SDA C...

Страница 31: ...of SM8250 GPIO AA Connects to GPIO_64 of SM8250 GPIO BB Connects to GPIO_27 of SM8250 PM GPIO A Connects to GPIO_6 of PM8150L Can be configured as PWM signal PM GPIO B Connects to GPIO_10 of PM8150L C...

Страница 32: ...SI_LS3 SSC QUP2 27 SPI2_MISO_LS3 SSC QUP2 29 SPI2_ACCEL_CS_LS3 SSC QUP2 31 SPI2_CS1 SSC QUP2 33 SPI3_CS1 SSC QUP5 35 VREG_L8C_1P8 37 VDC_5V A board DC buck power 5V 39 VBAT A board DC buck power 4 2V...

Страница 33: ...5C_1P8 40 GND 42 GND 44 SPI3_CS2 SSC QUP5 46 GPIO XX SSC QUP4 4 3 1 SSC SPI C865 DEV KIT implements 2 SSC SPI interfaces for different sensors that connect to SM8250 processor sensor core Each SPIs ca...

Страница 34: ...t to SM8250 sensor core 2 2k resistors are used in SOM to pull signals up for each of the I2C lines per the I2C specifications The signals are I2C4_SDA Connects to SSC QUP0 of SM8250 SoC Be configured...

Страница 35: ..._L8C_1P8 Connects to L8 LDO of PM8250 PMIC Can be as sensor IO voltage source VDC_5V Connects to a board DC buck power 5V Can be as a 5V voltage source VBAT Connects to a board DC buck power 4 2V Can...

Страница 36: ...onnector pin out PIN 96Boards Signals Note 1 SD_DAT0 SDC4_DATA0 3 SD_DAT1 SDC4_DATA1 5 SD_DAT2 SDC4_DATA2 7 SD_DAT3 SDC4_DATA4 9 SD_SCLK SDC4_SCLK 11 SD_CMD SDC4_CMD 13 GND 15 CLK0 CSI0_MCLK 17 CLK3 C...

Страница 37: ...DSI0_D3_P_HS1 47 DSI0_D3_M_HS1 49 GND 51 USB1_HS_DP_HS1 53 USB1_HS_DM_HS1 55 GND 57 NC 59 NC PIN C865 Dev Kit Signals Note 2 CSI0_C_P 4 CSI0_C_M 6 GND 8 CSI0_D0_P 10 CSI0_D0_M 12 GND 14 CSI0_D1_P 16...

Страница 38: ...0 GND 32 CCI_I2C_SCL0 34 CCI_I2C_SDA0 36 CCI_I2C_SCL1 38 CCI_I2C_SDA1 40 GND 42 CSI3_D0_P 44 CSI3_D0_M 46 GND 48 CSI3_D1_P 50 CSI3_D1_M 52 GND 54 CSI3_C_P 56 CSI3_C_M 58 GND 60 RESERVED Can be pull up...

Страница 39: ...terfaces are optional CSI0 interface can be up to four lanes while CSI1 is up to two lanes The current C865 DEV KIT board implementation supports a full 4 lane MIPI CSI interface on CSI0 and two lanes...

Страница 40: ...grammable clock interfaces to be provided on the High Speed Expansion Connector These clocks may have a secondary function of being CSI0_MCLK and CSI1_MCLK If these clocks can t be supported by the So...

Страница 41: ...GPIO EE PCIE1_WAKE_N 19 GPIO FF PCIE2_RST_N 21 GPIO GG PCIE2_CLK_REQ_N 23 GPIO HH PCIE2_WAKE_N 25 GND 27 CLK1 CSI1_MCLK 29 CLK2 CSI2_MCLK 31 GND 33 CSI2_C_P 35 CSI2_C_M 37 GND 39 CSI2_D0_P 41 CSI2_D0...

Страница 42: ..._P 10 CSI1_D0_M 12 GND 14 CSI1_D1_P 16 CSI1_D1_M 18 GND 20 CSI1_D2_P 22 CSI1_D2_M 24 GND 26 CSI1_D3_P 28 CSI1_D3_M 30 GND 32 SPI1_CLK QUP14 34 SPI1_CS QUP14 36 SPI1_MOSI QUP14 38 SPI1_MISO QUP14 40 CL...

Страница 43: ...for CSI2 CLK4 CSI4_MCLK GPIO98 for CSI4 and CLK5 CSI5_MCLK GPIO99 for CSI5 These signals are driven at 1 8V 5 2 3 SPI The C865 DEV KIT implements another SPI interface on the Secondary High Speed Expa...

Страница 44: ...E1 Reset GPIO DD Connects to GPIO_83 of SM8250 SoC Can be configured as PCIE1 Clock Request GPIO EE Connects to GPIO_84 of SM8250 SoC Can be configured as PCIE1 Wake GPIO FF Connects to GPIO_85 of SM8...

Страница 45: ...nals Note 1 CSI4_C_P 3 CSI4_C_M 5 CSI4_D0_P 7 CSI4_D0_M 9 GND 11 CSI4_D1_P 13 CSI4_D1_M 15 CSI4_D2_P 17 CSI4_D2_M 19 CSI4_D3_P 21 CSI4_D3_M 23 GND 25 CSI3_D2_P 27 CSI3_D2_M 29 CSI3_D3_P 31 CSI3_D3_M 3...

Страница 46: ...2_RF_CLK1 59 PMK8002_RF_CLK2 PIN C865 DEV KIT Signals Note 2 GND 4 PCIE1_RX1_M 6 PCIE1_RX1_P 8 PCIE1_TX1_M 10 PCIE1_TX1_P 12 GND 14 PCIE2_REFCLK_M 16 PCIE2_REFCLK_P 18 PCIE2_RX0_M 20 PCIE2_RX0_P 22 PC...

Страница 47: ...ctor supports 2 4 lane MIPI CSI bus MIPI CSI4 MIPI CSI5 and 2 data lane on MIPI CSI3 All MIPI CSI signals are routed directly to from the SM8250 5 3 2 Clock The C865 DEV KIT implements another 2 RF cl...

Страница 48: ...ntation C865 DEV KIT uses five buck regulators U0700 U0701 U0800 U0801 as the main power suppliers for C865 DEV KIT provide 4 2V for 865 SOM 4 2V 5V and 3 3V for peripherals in C865 DEV KIT U0700 and...

Страница 49: ...peripheral will not enable S W can enable it after 865 SOM is powered on 3 3V 5V for IO peripheral same as 4 2V for IO peripheral These 3 power rails are controlled via one same signal 6 4 Power Measu...

Страница 50: ...www thundercomm com 50 the resistor Dividing this measurement by 0 01 will give you the amount of the current...

Страница 51: ...press hold While the device is awake press and hold the Power button 20 see Section 1 2 2 for longer than 15 seconds to Power OFF the device Once OFF press and hold the Power button 20 see Section 1 2...

Страница 52: ...User LED 1 4 The four user LEDs are surface mount green LEDs 0603 size located between two USB Type A connectors and labeled USER LEDS 3 2 1 0 7 2 2 Wi Fi status The C865 DEV KIT Wi Fi LED is located...

Страница 53: ...lopment board see Section 1 2 2 17 Switch 1 BOOT_CONFIG 1 GPIO_27 Switch 2 BOOT_CONFIG 2 GPIO_47 Switch 3 BOOT_CONFIG 3 GPIO_76 Switch 4 BOOT_CONFIG 0 GPIO_128 When set to ON will disable WDOG when se...

Страница 54: ...www thundercomm com 54 9 Mechanical specification...

Страница 55: ...www thundercomm com 55...

Страница 56: ...t Number Connector MPN MPN of Mate High Speed Conn 1 2 3 FCI 61082 061409LF FCI 61083 064402LF Low Speed Conn 1 LS1 Molex 87381 4063 FCI 57202 G52 20LF Low Speed Conn 2 3 LS2 3 Samtec CLP 123 02 L D P...

Страница 57: ...3 0 gen3 1L USB 3 0 x1 GPIO x 8 HS3 1 x 60 pin high speed connector 4L MIPI CSI x 2 4L MIPI CSI x1 plus 2L CSI in HS1 RF CLK x 2 2L PCIe 3 0 x 1 2L PCIe 3 0 x 1 plus PCIe 1L in HS2 4L MIPI DSI x 1 LS...

Страница 58: ...www thundercomm com 58 Audio 4 digital PDM mics that interface directly to SM8250 chipset Speaker connectors 10 1 2Board views Top view Bottom view...

Страница 59: ...zanine is designed to connect the cellular networks adopts 5G M 2 key B modules which offers 5G sub6 or mmWave coverage 10 2 1Technical specifications Component Description Expansion interface HS1 1 x...

Страница 60: ...S2 4L MIPI DSI x 1 LS1 1 x 96boards 40 pin low speed connector UART x 2 SPI I2S PCM I2C x 2 GPIO x 12 DC powers LS2 1 x 96boards 40 pin low speed connector Speaker x 2 DMIC I F x 3 CAN I2S GPIOs PWM A...

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