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ETC210
First issue 07 / 03
IA001- MSP34X0 / X1G
SC
28
20
21
17
18
23
6
25
26
29
ART1
SCART2
SCART1
SCART2
SCART4
SCART3
MO
47
50
51
45
41
38
35
36
39
42
44
6
12
NO
Headphone
I
2
S
Loud-
Subwoofer
I
2
S1
I
2
S2
Sound IF1
So
MSP 34X1G
und IF
speaker
S
o
u
rce Sel
ect
Loud-
De-
modulator
Headphone
Sound
Processing
speaker
Sound
Processing
DAC
DAC
ADC
DAC
ADC
SCART
DSP
Input
Select
Pre-
processing
SCART
Output
Select
Prescale
Prescale
DAC
IR001- ST92R195B
ST92r195B
2
ME
MOR
Y
B
U
S
I/O
PORT 0
R
E
G
IST
ER
B
U
S
VO LTAGE
SYNTHESIS
P. W.M.
D/A CON-
VERTER
SPI
I/O PORT 4
P. W.M
Output
I/O
PORT 5
(SPI)
TELETEXT
DATA
SLICER
SYNC.
EXTRAC-
TION
8K Bytes
TDSRAM TRI
STANDARD
TIMER
TIMING S
CTRL UNIT
16-BIT
TIMER/
WATCHDOG
VPS/WSS
DATA
SLICER
I/O PORT 2
ADC/VS
ADC
CVBS1
I/O
PORT 3
CSO
SYNC
CONTROL
VSYNC
HSYNC/
CSYNC
ON
SCREEN
DISPLAY
PLL
PXFM/
NMI
INT[7:0]
256 bytes
Register File
ST9+ CORE
8/16 bits
CPU
Interrupt
Management
RCCU
Oscin
Oscout
RESET
P0[2:0]
3
AIN1
WSCR
WSCF
CVBS2
TXCF
6
AIN2
AIN3
VS01
VS02
4
RESET0
CSO
R/G/B/FB/TSLU
8
PWM[7:0]
EXTRG
SDO/SDI
SCK
AIN4
STOU T
1 Kbyte
RAM
1 Kbyte
RAM
PLL
INTEGRATED CIRCUITS BLOCK DIAGRAMS - SYNOPTIQUES INTERNES DES CIRCUITS
INTEGRES - INTEGRIERTE SCHALTUNGEN BLOCKSCHALTBILDER - SCHEMA A
BLOCCHI DEI CIRCUITI INTEGRATI - VISTA INTERNA DE LOS CIRCUITOS INTEGRADOS