THine THCV245 A, Руководство пользователя

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Preliminary
THCV245A_Rev.0.90_E
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6.14 V-by-One® HS VSYNC generation
Setting of V-by-One® HS VSYNC output is configurable by 2-wire access on internal register.
Internally generated VSYNC (R_VS_MODE=1) follows Figure 8.
Table 25. V-by-One® HS output VSYNC setting
Figure 8. Internally generated VSYNC
Addr(h) Bits Register w idth R/W Description Default
0x1002 [3:2] R_FS_FE_SYNCEN 2 R/W
V-by-One® HS Vsync generation Enable at MIPI FS/FE
(active only w hen R_VS_MODE=0)
00:Vsync pulse at both FS and FE (THCV242-Q default)
01:Vsync pulse at FS only
10:Vsync pulse at FE only
11:no Vsync pulse at FS nor FE
2'h0
0x1004 [1] R_VSYNC_POL 1 R/W
V-by-One® HS Vsync polarity
0:High pulse (High active) (THCV242-Q default)
1:Low pulse (Low active)
1'h0
0x1007 [3] R_VS_MODE 1 R/W
V-by-One® HS VSYNC output timing mode
0:MIPI FS/FE timing direct use mode (THCV242-Q default)
1:internally generated timing mode
1'h0
0x1007 [2:0] R_VS_OFFSET 3 R/W
V-by-One® HS internally generated VSYNC of fset
of fset f rom FE = calculatedVS-HTOTAL x R_VS_OFFSET
3'h0
0x1008 [7:0] R_VS_WIDTH_PIX 8 R/W
V-by-One® HS internally generated Htotal setting
Generated Htotal:calculatedVS-HTOTAL = R_VS_WIDTH_PIX x 16
8'h00
0x1009 [4:2] R_VS_WIDTH_LINE 3 R/W
V-by-One® HS internally generated VSYNC pulse w idth
VSYNC pulse w idth = calculatedVS-HTOTAL x
R_VS_WIDTH_LINE
3'h0
FE
offset LINE 1 offset LINE 2 offset LINE m VSYNC LINE 1 VSYNC LINE 2 VSYNC LINE n
V-by-One® HS
PCLK
MIPI FE
Internal VSYNC
generation counter
Internally generated
V-by-One® HS VSYNC
( For example, R_VSYNC_POL=0 )
calculatedVS-HTOTAL = R_VS_WIDTH_PIX x 16 x PCLK
calculatedVS-HTOTAL x R_VS_OFFSET(=m) calculatedVS-HTOTAL x R_VS_WIDTH_LINE(=n)