THine THCV242, Руководство пользователя, Страница: 29 / 53

THCV242_ Rev.2.00_E
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6.5. MIPI
Deserializer and CSI-2 Formatter
6.5.1.1. PLL setting
PLL setting is required. PLL setting set R_PLL_SETTING[47:0] is related with Main-Link data-rate.
Figure 1 Reference clock supply basic method
PLL_SETTING[47:0] must be selected proper to meet below constraints.
Table 1 PLL constraints
Pixel clock frequency made by PLL is calculated as below.
1st Output Divider 2nd Output Divider F(MIPI output)
1-7 x 1/OutDiv1 x 1/OutDiv2 80-1200MHz
1-7 1-7
FeedBack Divider
x 1/FBDiv
20-130
F(PFD)
15< MHz
PLL Configuration
F(VCO)
F(Main-Link input) Reference Divider
PFD VCO
500-1300MHz
15-100MHz x 1/RefDiv
symbol discription min typ max unit
F(IN) PLL input pixel clock frequency 10 - 133.3 MHz
RefDiv Reference Divider value 1 - 7 -
FBDiv FeedBack Divider value 20 - 130 -
OutDiv1 1st Output Divider value
(OutDiv1 must be >= OutDiv2)
1 - 7 -
OutDiv2 2nd Output Divider value
(OutDiv1 must be >= OutDiv2)
1 - 7 -
F(PFD) PFD frequency 10 - MHz
F(VCO) VCO frequency 500 - 1300 MHz
F(OUT) PLL output pixel clock frequency 80 - 1200 MHz
[PCLK.output] = [F(MIPI output)] =
[RefDiv] x [OutDiv1] x [OutDiv2]
[F(Main-Link input)] x [FBDiv]
MIPI High Speed mode DDR output clock per lane = [F(MIPI output)] / 2 (MHz)
[PCLK.input] = Pixel clock recovered on V-by-One® HS per lane = [F(Main-Link input)] = F(IN)
F(VCO) =
=
[RefDiv] x [OutDiv1] x [OutDiv2]
[FBDiv]
[F(Main-Link input)]
[F(MIPI output)]
MIPI data-rate per lane (Mbps)
[F(Main-Link input)] = Main-Link data-rate per lane / (Byte mode x 8 x 10/8)
= [F(MIPI output)] (MHz)
[RefDiv]
[F(Main-Link input)] x [FBDiv]
= F(OUT)
= MIPI High Speed mode data-rate per lane