Texas Micro AI5VP, Руководство пользователя

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Chapter 6 BIOS Configuration
AI5VP/AI5VPB User’s Manual 39
2 Bank PBSRAM
This field sets the burst cycle for the two banks of PBSRAM. The options
are
3-1-1-1 and 2-1-1-1 . The default setting is 3-1-1-1 .
Read Pipeline
When enabled, this field supports PBSRAM read pipeline function. The
default setting is
Enabled .
Write Pipeline
When enabled, this field supports PBSRAM write pipeline function. The
default setting is
Enabled .
Cache Timing
This field sets the timing of the cache in the system. The options are Fast
and Fastest . By default, this field is set to Fast .
Video BIOS Cacheable
When enabled, access to video BIOS addressed at C0000H to C7FFFH are
cached, provided that the cache controller is enabled.
System BIOS Cacheable
When enabled, access to the system BIOS ROM addressed at
F0000H-FFFFFH are cached, provided that the cache controller is enabled.
Memory Hole at 15MB Addr.
In order to improve performance, certain space in memory can be reserved
for ISA cards. This field allows you to reserve 15MB to 16MB memory
address space to ISA expansion cards. This makes memory from 15MB
and up unavailable to the system. Expansion cards can only access memory
up to 16MB. By default, this field is set to
Disabled.
On Chip USB
This field allows you either to enable or disable USB function. By default,
this field is set to
Disabled.