Texas Micro AI5VP, Руководство пользователя

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Chapter 6 BIOS Configuration
38 AI5VP/AI5VPB User’s Manual
6.5 Chipset Features Setup
This Setup menu controls the configuration of the motherboard chipset.
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
DRAM Auto Configuration : 70 ns OnChip USB : Disabled
DRAM Timing Control : Auto
SDRAM Cycle Length : 3
SDRAM Bank Interleave : Disabled
Sustained 3T Write :
Enabled
2 Bank PBSRAM : 3-1-1-1
Read Pipeline : Enabled
Write Pipeline
:
Enabled
Cache Timing : Fast
Video BIOS Cacheable : Enabled
System BIOS Cacheable : Disabled ESC : Quit
Ç È Æ Å
: Select Item
Memory Hole At 15MB :
Disabled
F1 : Help PU/PD/+/- : Modify
F5 : Old Values (Shift) F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
DRAM Auto Configuration
This field predefined values for DRAM, cache timing according to CPU
type and system clock. When this field is enabled, the predefined items will
become read-only.
DRAM Timing Control
The DRAM timing is controlled by the DRAM Timing Registers. The
timing type is dependent on the system design. Slower rates may be
required in some system designs to support loose layouts or slower
memory.
SDRAM Cycle Length
This field sets the length the SDRAM cycle. The options are 2 and 3 . By
default, this field is set to 3.
SDRAM Bank Interleave
This field allows support for SDRAM bank interleave. By default, this
field is set
Disabled .
Sustained 3T Write
This field allows support for PBSRAM sustained 3T write. By default, this
field is set
Enabled .