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3
SPRUI94 – January 2017
Copyright © 2017, Texas Instruments Incorporated
List of Figures
List of Figures
1
XDS110 Probe High-Level Block Diagram
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2
Debug Connection (CTI-20) Pin Mapping
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3
AUX Connection Signal Mapping
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4
Setup Power Source Control
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5
Probe-Supplied Power and Voltage Level
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6
Enabling ET on Connect
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7
Selecting XDS110
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8
EnergyTrace Overview
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9
EnergyTrace and the Toolbar
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10
EnergyTrace Dynamic View
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11
xdsdfu Screenshot
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12
dbgjtag Screenshot JTAG Integrity Test
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13
dbgjtag SWD Integrity Test
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14
dbgjtag Scan Path Test
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List of Tables
1
Acronyms and Definitions
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2
Expansion Header Signal Mapping
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3
LEDs and Probe Operational States
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4
CTI to Other Adaptor Pin Mapping
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5
Auxiliary Breakout Board Signal Mapping
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