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2.5
VLYNQ Functional Description
Address
translation
commands
Outbound
Outbound
command
FIFO
data
Return
FIFO
data
FIFO
Return
command
Inbound
FIFO
Registers
translation
Address
TxSM
8B/10B
encoding
Serializer
commands
Inbound
RxSM
Deserializer
decoding
8B/10B
Serial
TxData
Serial
TxClk
Serial
RxClk
Serial
RxData
Master
config bus
interface
System clock
VLYNQ clock
Slave
config bus
interface
(FIFO3)
(FIFO2)
(FIFO0)
(FIFO1)
Peripheral Architecture
The VLYNQ core supports both host-to-peripheral and peer-to-peer communication models and is
symmetrical. The VLYNQ module structure is shown in
Figure 4
.
Figure 4. VLYNQ Module Structure
The VLYNQ core module implements two 32-bit configuration bus interfaces. Transmit operations and
control register access require the slave configuration bus interface. The master configuration bus
interface is required for receive operations. Converting to and from the 32-bit bus to the external serial
interface requires serializer and deserializer blocks.
8b/10b block coding encodes data on the serial interface. Frame delineation, initialization, and flow control
use special overhead code groups.
FIFOs buffer the entire burst on the bus for maximum performance, thus minimizing bus latency. Using
write operations of each VLYNQ module interfaced is typically recommended to ensure the best
performance on both directions of the link.
SPRUE36A – September 2007
VLYNQ Port
13
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