Design Note: J37, J38, J39, J40, J42, J43,
J45, J46, J51, and J59 should have default
trace run between pins 1 and 2 on the top
layer.
These should be thick power traces.
Design Note: VDDA3P3 and VDDS3P3 are tied
together in this design.
C27
.1uF
C29
.1uF
1
2
J45
VDDA_3.3V
VDD_1.8V_TUSB6020
VBUS
C38
.01uF
VDD_1.8V
C40
.1uF
C44
.01uF
VDD_MMOD_CONNECTOR
C45
1uF
VOUT2_REGULATOR
C63
10uF
C28
.01uF
C30
.01uF
C37
.1uF
1
2
J43
VBUS_REGULATOR
1
2
J44
1
2
J46
C65
10uF
VDD_MMOD_REGULATOR
SS: 3.3R
SS: 1.8R
SS: 1.8C
SS: VBUSR
SS: VDD1.8
1
2
J51
VDDCM_1.5V
VDD_1.5V
C61
10uF
1
2
J37
C59
.01uF
1
2
J38
1
2
J39
1
2
J40
C57
.1uF
C56
.01uF
1
2
J42
C41
.1uF
C39
.01uF
VOUT3_REGULATOR
VDDA_1.5V
C53
.01uF
C64
10uF
C54
.1uF
C60
.1uF
SS: VDDD
SS: VDDCM
SS: VDD
SS: 1.5R
SS: VDDA
C58
10uF
C62
10uF
C42
.01uF
C43
.1uF
VDDD_1.5V
TUSB6020 Schematics
www.ti.com
Figure 1-7. Power Jumpers
14
TUSB6020 EVM
SLAU242 – February 2008