1.7
TUSB6020 Schematics
Design Note: X1 should be placed close to U1
Design Note: X2, C2 and C3 should be placed close to U1
Design Note: R2 should be placed close to U1
Design Note: Pull-down
resistors are required on
"No Connect" signals:
A8, B7, B8, B9, C6, C7,
C8, D6, D8, E7, G4 and
J5.
J23
PAD
J24
PAD
R112
1K
J26
PAD
J25
PAD
J27
PAD
J28
PAD
R114
1K
J29
PAD
J30
PAD
R123
1K
J31
PAD
J32
PAD
R106
1K
R108
1K
J21
PAD
R110
1K
J22
PAD
R115
1K
R113
1K
R111
1K
R109
1K
R107
1K
1
2
J16
SLEEP
R4
1K
R30
1K
VDDA_3.3V
VLYNQ_TXD[3..0] 7
VLYNQ_TXD2
VLYNQ_TXD3
VLYNQ_TXD0
VLYNQ_TXD1
VLYNQ_RXD3
VLYNQ_RXD1
VLYNQ_RXD2
VLYNQ_RXD0
VLYNQ_RXD[3..0]
7
VLYNQ_CRUN
7
VLYNQ_CLK 7
VSS1
A2
VSS2
A6
VSS3
B4
RSVD4
B9
VSS5
E5
VLYNQ_CRUN
E9
VSS6
G1
VLYNQ_TXD1
G9
VSS9
J2
NC4
J4
VSS10
J8
VSSREF
B1
VSSCM1P5
D3
VSSA3P3
E4
VSSA1P5
E1
VSSD1P5
F4
R1
C2
XO
A3
XI
A4
VDD15_2
A1
VDD15_3
A9
VDD15_4
B3
VDD15_5
C5
VSS4
D9
VDDCM1P5
D2
VLYNQ_CLK
F9
VDD15_6
J3
VDDD1P5
F1
VDDA1P5
E3
DP
D1
DM
E2
VBUS
F3
ID
F2
VDD18_1
A7
VDD18_2
B5
VLYNQ_TXD0
H9
VDD18_4
J1
VLYNQ_RXD3
J6
VDDA3P3
C1
NC1
F6
GPIO3
E6
NC2
G5
VDDS3P3_2
G6
NC3
H5
VLYNQ_RXD2
H6
VLYNQ_RXD0
H7
VLYNQ_TXD2
H8
VDDS3P3_1
F8
VLYNQ_TXD3
F7
RSVD9
D8
RSVD6
C7
VDD15_1
D7
RSVD7
C8
RSVD2
B7
RSVD3
B8
GPIO0
H4
GPIO1
D5
GPIO2
B6
VDD18_3
E8
GPIO4
C4
RSVD10
E7
GPIO6
F5
GPIO7
B2
VDDS3P3_3
J9
RSTn
H1
CPEN
H2
SLEEP
H3
1.5V_SWEN
G2
3.3V_SWEN
G3
RSVD11
G4
VSS7
G7
VSS8
G8
RSVD1
A8
CLKIN
A5
GPIO5
C9
RSVD8
D6
TEST
D4
VLYNQ_RXD1
J7
RSVD12
J5
RSVD5
C6
U1
TUSB6020
DM
3
DP
3
ID
3
VBUS
3.3V_SWEN
VDDD_1.5V
1.5V_SWEN
VDDCM_1.5V
VDDA_1.5V
VDDA_3.3V
VDD_1.8V_TUSB6020
VDD_1.5V
1
2
J10
1
2
J15
CP_EN
2
GPIO2
6
GPIO0
6
RESETn
2
GPIO1
6
GPIO4
6
GPIO5
6
GPIO6
6
GPIO3
6
GPIO7
6
J33
PAD
J34
PAD
J35
PAD
R124
1K
1
2
X2
24 MHz, CL = 20pF
C2
33pF
C3
33pF
R2
10.7K 1%
J36
PAD
J20
PAD
J54
PAD
J55
PAD
J56
PAD
J57
PAD
R105 10K
J58
PAD
VDD_1.8V
VCC
4
EN
1
GND
2
OUT
3
X1
19.2 MHz, CSX-1
C1
.01uF
TUSB6020 Schematics
www.ti.com
Figure 1-3. TUSB6020
10
TUSB6020 EVM
SLAU242 – February 2008
