Texas Instruments TSW14J57EVM, Руководство пользователя

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Hardware Configuration
9 SLWU092 – April 2017
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TSW14J57 JESD204B High-Speed Data Capture and Pattern Generator Card
User's Guide
Table 4. FMC+ Connector Description of the TSW14J57 (continued)
FMC+ Signal Name FMC+ Pin Standard JESD204
Application Mapping
Description
TX0_P/N C2 and C3 Lane 0± (C
→
M) JESD Serial data transmitted from carrier and received by
mezzanine
TX1_P/N A22 and A23 Lane 1± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX2_P/N A26 and A27 Lane 2± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX3_P/N A30 and A31 Lane 3± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX4_P/N A34 and A35 Lane 4± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX5_P/N A38 and A39 Lane 5± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX6_P/N B36 and B37 Lane 6± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX7_P/N B32 and B33 Lane 7± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX8_P/N B28 and B29 Lane 8± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX9_P/N B24 and B25 Lane 9± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX10_P/N Z24 and Z25 Lane 10± (C
→
M) JESD Serial data transmitted from carrier and received by
mezzanine
TX11_P/N Y26 and Y27 Lane 11± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX12_P/N Z28 and Z29 Lane 12± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX13_P/N Y30 and Y31 Lane 13± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX14_P/N Z8 and Z9 Lane 14± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
TX15_P/N Y6 and Y7 Lane 15± (C → M) JESD Serial data transmitted from carrier and received by
mezzanine
GBTCLK0_M2C_P/N D4 and D5 DEVCLKA± (M → C) Primary carrier-bound reference clock required for FPGA
giga-bit transceivers. Equivalent to device clock.
GBTCLK1_M2C_P/N B20 and B21 Alt. DEVCLKA± (M → C) Alternate Primary Carrier-bound reference clock required for
FPGA giga-bit transceivers. For use when DEVCLKA (M
→
C) is not available
GBTCLK5_M2C_P/N Z20 and Z21 Alt. (M → C) Alternate Primary Carrier-bound reference clock required for
FPGA giga-bit transceivers. For use when DEVCLKA (M
→
C) is not available
Device Clock, SYSREF, and SYNC
CLK_LA0_P/N G6 and G7 DEVCLKB± (M → C) Secondary carrier-bound device clock. Used for special FPGA
functions such as sampling SYSREF
LA01_P/N_CC D8 and D9 DEVCLK± (C → M) Mezzanine-bound device clock. Used for low noise
conversion clock
SYSREF_P/N G9 and G10 SYSREF± (M → C) Carrier-bound SYSREF signal
LA05_P/N D11 and D12 SYSREF± (C → M) Mezzanine-bound SYSREF signal
RX_SYNC_P/N G12 and G13 SYNC± (C → M) ADC mezzanine-bound SYNC signal for use in class 0/1/2
JESD204 systems
TX_SYNC_P/N F10 and F11 DAC SYNC± (M
→
C) Carrier-bound SYNC signal for use in class 0/1/2 JESD204
systems
TX_ALT_SYNC_P/N F19 and F20 Alt. DAC SYNC± (M → C) Alternate carrier-bound SYNC signal for use in class 0/1/2
JESD204B systems
RX_ALT_SYNC_P/N H31 and H32 Alt. SYNC± (C → M) Alternate ADC mezzanine-bound SYNC signal. For use when
SYNC (C
→ M) is not available