Hardware Configuration
10
SLWU092 – April 2017
Copyright © 2017, Texas Instruments Incorporated
TSW14J57 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide
Table 4. FMC+ Connector Description of the TSW14J57 (continued)
FMC+ Signal Name
FMC+ Pin
Standard JESD204
Application Mapping
Description
SYNC
K22
DAC SYNC (M
→
C)
Carrier-bound CMOS-level SYNC signal for use in class 0/1/2
JESD204 systems
Special Purpose I/O
PG_M2C_A
F1
Power good from mezzanine to carrier
CLK0_M2C_P/N
H4 and H5
GPIO clock
CLK1_M2C_P/N
G2 and G3
GPIO clock
All other signals not mentioned in
can be used as general purpose I/O, either as single-ended
signals or differential pairs. The ANSI/VITA 57.4 standard assigns voltages to certain pins. These are
labeled as 12V, 3P3V, and VADJ nets on the connector page of the schematic. On the TSW14J57, these
pins are connected to test points to allow the user to provide voltages at these pin locations.
3.3.3.3
JTAG Connectors
The TSW14J57EVM includes three industry-standard JTAG connectors; one that connects to the JTAG
ports of the FPGA, one that connects to the JTAG pins of the Cypress FX3 USB Contoller and the other
that connects to the programming pins of the power monitor/sequencer device. Jumpers on the
TSW14J57EVM allow for the FPGA to be programmed from the JTAG connector or the USB interface.
JTAG connectors J3 and J7 are to be used for troubleshooting only. The board default setup is with the
FPGA JTAG pins connected to JTAG connector J3. The FPGA can be programmed using this connector if
the MSEL inputs are set to the proper logic levels. These are set by solder jumpers SJP1-3. Consult the
Intel
®
PSG data sheet for more information regarding JTAG programming. The FPGA also has the parallel
programming inputs connected to the USB 3.0 controller. With SJP1-3 in the default postions, this allows
the FPGA to be programmed by the HSDC Pro software GUI. Every time the TSW14J57EVM is powered-
down, the FPGA configuration is removed. The user must program the FPGA through the GUI after every
time the board is powered-up. This device is programmed at power-up using the factory pre-programmed
flash device U10. JTAG connector J7 is used to program the TI UCD90120A power monitor/sequencer
device. This device is pre-programmed at the factory and this interface should only be used for
troubleshooting.
3.3.3.4
USB I/O Connection
Control of the TSW14J57EVM is through USB 3.0 connector J4. This provides the interface between
HSDC Pro GUI running on a PC using the Microsoft
®
Windows
®
operating system and the FPGA. For the
computer, the drivers needed to access the USB port are included on the HSDC Pro GUI installation
software that can be downloaded from the web. The drivers are automatically installed during the
installation process. On the TSW14J57EVM, the USB port is used to identify the type and serial number of
the EVM under test, load the desired FPGA configuration file, capture data from ADC EVMs, and send
test pattern data to the DAC EVMs.
