DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform
18
SLAU580B – June 2014 – Revised September 2016
Copyright © 2014–2016, Texas Instruments Incorporated
TSW14J10 FMC-USB Interposer Card
For the DAC3XJ8X GUI, the REFCLK is provided by
CLKout 0
and the Core clock is provided by
CLKout
12
. Notice that the default setting for
CLKout 12
is
Group Powerdown
, as shown in
.
Figure 9. LMK04828 Clock Outputs Menu
Since the DAC Clock is 368.64 MHz, to provide a REFCLK of 368.64 MHz, change the
DCLK Divider
for
CLKout 0
to “8”.
To generate a Core clock of 184.32 MHz, set the
DCLK Divider
for
CLKout 12
to “16”. Also, remove the
checkmark from the
Group Powerdown
box to enable this output.
