Texas Instruments TSW12QJ1600, Руководство пользователя

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DA[15:0]
SYNC
FPGA_GBT_CLK
ADC_SYSREF
TSW12QJ1600
CLK
SYSREF
DA[15:0]
FMC+
SYNC
TRIGOUT
FPGA_CLK PLLREFO
50MHz
VCXO
SE_CLK
J2
EXT CLK
(50-500MHz)
DA[15:0]
SYNC
FPGA_GBT_CLK
ADC_SYSREF
TSW12QJ1600
CLK
SYSREF
DA[15:0]
FMC+
SYNC
TRIGOUT
FPGA_CLK PLLREFO
50MHz
VCXO
SE_CLK
Customizing the EVM for Optional Clocking Support
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20 SLAU796 – July 2020
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HSDC Pro Settings for Optional ADC Device Configuration
Figure B-1. Onboard 50M Ref to ADC PLL System Block Diagram
B.2.2 "Ext Ref to ADC PLL"
The reference signal for the ADC PLL is provided externally from External signal generator on SMP
labeled EXT CLK(J2) . The sampling clock is generate by ADC PLL, from this external provided PLL
reference signal. In this clocking mode ADC also generate the reference clock signal for FPGA. FPGA
takes this reference clock and generates the SYSREF signal for the ADC and feed it back to the ADC.
Figure B-2 shows the block diagram of Ext Ref to ADC PLL clocking option:
• Remove R231, and populate C27.
Figure B-2. Ext Ref to ADC PLL System Block Diagram