1
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D
D
C
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B
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A
A
1
2
TSU6721EVM
4/21/2014
HVL046A.SchDoc
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TSU6721EVM
Project Title:
Designed for:
Public Release
Assembly Variant:
Variant name not interpreted
© Texas Instruments
2014
Drawn By:
Engineer:
Ryan Land
Ryan Land
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpos
e, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Not in version control
SVN Rev:
HVL046
Number:
Rev:
A
micro-USB side
mini-USB (host) side
MSP-430_J9
MSP-430_J8
VCC (+3.3V)
Analog In
UART_HW _RX
UART_HW _TX
GPIO (INT)
SPI_A_SCLK
SPI_B_SCLK
GPIO (Cap Touch)
GPIO (Cap Touch)
GPIO (Cap Touch)
GND
Timer Out
GPIO (INT)
Test (SpyBi-W ire)
RESET
SPI_B_SIMO/I2C_SDA
SPI_B_SOMI/I2C_SCL
GPIO (Cap Touch)
GPIO (Cap Touch)
GPIO (Cap Touch)
1
2
3
4
5
6 7 8 9 10 1
1
J22
2 3 4
1
5
J5
J29
DM
Through path
1
2
3
J2
A
B
1
2
3
J4
ISET
BOOT
JIG
J26
TP1
TP2
TP3
GND GND GND
INTB
VDDIO
5
4
1
2
3
6
7
8
9
10
J8
5
4
1
2
3
6
7
8
9
10
J9
GND
GND
VBAT
D1
VDDIO
A2
VBUS
A5
OUT
A4
GND
E5
DP_HT
B1
DM_HT
C1
IDBP
D2
RxD
E1
TxD
E2
VBUS_CAP
C3
MIC
B4
GND
D3
GND
D4
S_R
C4
S_L
B3
DM
B5
SCL
C2
SDA
B2
DP
C5
ID
D5
INTB
A1
ISET
A3
JIG
E4
BOOT
E3
U1
TSU6721YFP
GND
1
2
3
4
5
6
7
8
9
10
11
J15
GND
GND
JIG
BOOT
ISET
INTB
2
3
4
1
5
J12
GND
DP_HT
DM_HT
IDBP
2
1 3
J25
GND
1
2
J23
S_L
S_R
TxD
RxD
S_L
S_R
MIC
VDDIO
VBAT
VBUS
0
R1
J10
J11
Green
D1
1
2
J1
GND
3V3
1
2
J3
GND
VDDIO
VBAT
3V3
1
2
3
J7
1
2
J6
GND
VBUS
V_USB
EXT
VDDIO
3V3
EXT
VBAT
3V3
EXT
VBUS
V_USB
RxD
TxD
INTB
ISET
BOOT
JIG
GND
GND
VBAT
VDDIO
GND
VBUS
SCL
SDA
3V3
GND
SDA
SCL
1
2
3
J18
10k
R5
VBAT
ISET
BOOT
JIG
1
2
J19
RxD
TxD
1
2
J20
SCL
SDA
RxD
TxD
SCL
SDA
INTB
OUT
OUT
VBUS_HT
1
2
J21
J28
1
2
J24
GND
VBUS_HT
VBUS_HT
VBUS_HT
OUT
LED
S_L
S_R
VBUS_HT
MIC
DP
0
R3
J13
0
R4
J14
ID
J17
MIC
J16
VBAT is power input to the board. 3V to 4.4 V.
VDDIO is logic power input to the board. 1.65 V to 3.6 V.
VBUS is secondary USB power to the board. 4 V to 6.5 V.
OUT
J27
VBUS
VBUS
10k
R7
10k
R8
0
R2
330
R9
GND
GND
V_USB
Maximum VBUS to OUT current is programmable (2 A default)
0.1µF
C4
1µF
C3
0.1µF
C2
1µF
C1
0.1µF
C6
1µF
C5
75.0
R6
10µF
C7
Schematic
4
Schematic
shows the schematic for the TSU6721EVM.
Figure 10. TSU6721EVM Schematic
15
SLVUA77 – May 2014
TSU6721EVM Micro-USB Switch Evaluation Module
Copyright © 2014, Texas Instruments Incorporated
