48
SLOS757G – DECEMBER 2011 – REVISED MARCH 2020
Product Folder Links:
Detailed Description
Copyright © 2011–2020, Texas Instruments Incorporated
6.14.1.2.4 Modulator and SYS_CLK Control Register (0x09)
describes the bit fields of the Modulator and SYS_CLK Control register. This register controls
the modulation input and depth, ASK/OOK pin control, and clock output to an external system (an MCU).
Default Value:
0x11, set at POR = H or EN = L at each write to the ISO Control register for all bits except
Clo1 and Clo0
The frequency of SYS_CLK (pin 27) is programmable by bits B4 and B5 of this register. The frequency of
the TRF7962A system clock oscillator is divided by 1, 2, or 4 resulting in available SYS_CLK frequencies
of 13.56 MHz, 6.78 MHz, or 3.39 MHz, respectively.
The ASK modulation depth is controlled by bits B0, B1, and B2. The range of ASK modulation is 7% to
30% or 100% (OOK). The selection between ASK and OOK (100%) modulation can also be done using
direct input OOK (pin 12). The direct control of OOK or ASK using the OOK pin is only possible if the
function is enabled by setting B6 = 1 (en_ook_p) in this register (0x09) and the ISO Control register (0x01,
B6 = 1). When configured this way, the MOD pin (pin 14) is used as input for the modulation signal.
Table 6-22. Modulator and SYS_CLK Control Register (0x09)
BIT NO.
BIT NAME
FUNCTION
DESCRIPTION
B7
Unused
B6
en_ook_p
1 = Enables external selection of
ASK or OOK modulation
0 = Default operation as defined
in bits B0 to B2 of this register
Enable ASK/OOK pin (pin 12) for change between any preselected
ASK modulation as defined by B0 to B2 and OOK modulation.
If B6 is set to 1, pin 12 is configured as:
1 = OOK modulation
0 = Modulation as defined in B0 to B2 (0x09)
B5
Clo1
SYS_CLK output frequency. B5
is the MSB.
Clo1
Clo0
SYS_CLK Output
0
0
Disabled
0
1
3.39 MHz
B4
Clo0
1
0
6.78 MHz
1
1
13.56 MHz
B3
en_ana
1 = Sets pin 12 (ASK/OOK) as
an analog output
0 = Default
For test and measurement purpose. ASK/OOK pin 12 can be used
to monitor the analog subcarrier signal before the digitizing with DC
level equal to AGND.
B2
Pm2
Modulation depth. B2 is the MSB.
Pm2
Pm1
Pm0
Modulation Type and Percentage
0
0
0
ASK 10%
0
0
1
OOK (100%)
B1
Pm1
0
1
0
ASK 7%
0
1
1
ASK 8.5%
1
0
0
ASK 13%
B0
Pm0
1
0
1
ASK 16%
1
1
0
ASK 22%
1
1
1
ASK 30%