Texas Instruments TRF3722 EVM, Руководство пользователя

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1
st
Write
clock
pulse
32
nd
Write
clock
pulse
t
w
CLOCK
DATA
LATCH
ENABLE
R
E
G
IS
T
E
R
W
R
IT
E
DB1
Address Bit1
DB2
Address Bit2
DB3
Address Bit3
DB29 DB30
DB0 (LSB)
Address Bit0
t
su3
t
su1
t
h
t
(CLK)
DB31 (MSB)
t
(CL)
t
(CH)
t
su2
End of Write
Cycle pulse
33
TRF3722
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7 Parameter Measurement Information
7.1 Serial Interface Timing Diagram
The TRF3722 features a four-wire serial programming interface (4WI) that controls an internal 32-bit shift register
with seven parallel registers. There are total of three signals that must be applied: the clock (CLK), the serial data
(DATA), and the latch enable (LE). The fouth signal is the read back (RDBK) signal. The serial data (DB0-DB31)
are loaded least significant bit (LSB) first, and read on the rising edge of the CLK. LE is asynchronous to the CLK
signal; at its rising edge, the data in the shift register are loaded into the selected internal register.
Figure 130
shows the timing diagram the 4WI. Table 1 lists the 4WI timing for the write operation.
Figure 130. 4WI Writing Timing Diagram
Table 1. 4WI Timing for Write Operation
MIN TYP MAX UNIT
t
h
Hold time, data to clock 20 ns
t
SU1
Setup time, data to clock 20 ns
t
CH
Clock low duration 20 ns
t
CL
Clock High duration 20 ns
t
SU2
Setup time, clock to enable 20 ns
t
CLK
Clock period 50 ns
t
W
Enable Time 50 ns
t
SU3
Setup time, Latch to Data 70 ns