Texas Instruments TPS7A53EVM-080, Руководство пользователя, Страница: 3 / 17

1 Introduction
The Texas Instruments TPS7A53EVM-080 evaluation module (EVM) helps designers evaluate the operation
and performance of the TPS7A53A-Q1 LDO voltage regulator. As shown in
Table 1-1 , the TPS7A53EVM-080
contains one TPS7A53A-Q1 LDO voltage regulator in the RTJ package. An optional load transient circuit is also
included to assist the user with high-speed load transient testing. To simplify current measurements, an input
current loop is included.
Table 1-1. Device Information
EVM ORDERABLE NUMBER V
OUT
PART NAME PACKAGE
TPS7A53EVM-080 1.0 V TPS7A5310AQWRTJRQ1 20-pin RTJ
Table 1-2 lists the related documentation available through the Texas Instrument web site at www.ti.com .
Table 1-2. Device Information
Device Literature Number
TPS7A53A-Q1 SBVS412
2 Setup
This section describes the jumpers and connectors on the EVM, and how to properly connect, set up, and use
the TPS7A53EVM-080.
Section 2.1 and Section 2.3 describe the test setup and operation for the TPS7A53A-Q1
LDO. Section 2.2 and Section 2.4 describe the test setup and operation of the optional load transient circuit.
2.1 LDO Input/Output Connector Descriptions
2.1.1 VIN and GND
VIN and GND are the connection terminals for the input supply. The VIN terminal is the positive connection, and
the GND terminal is the negative (that is, ground) connection.
2.1.2 BIAS and GND
BIAS and GND are the connection terminals for the bias supply. The BIAS terminal is the positive connection,
and the GND terminal is the negative (that is, ground) connection.
2.1.3 VOUT and GND
VOUT and GND are the connection terminals for the output load. The VOUT terminal is the positive connection,
and the GND terminal is the negative (that is, ground) connection.
2.1.4 EN
EN is a 3-pin header used to enable or disable the TPS7A53A-Q1.
The center pin of the 3-pin header is tied to the TPS7A53A-Q1 EN input. When the 2-pin shunt is placed across
the two rightmost pins of the header, V
IN
is shorted to EN and the TPS7A53A-Q1 is enabled. When the 2-pin
shunt is placed across the two leftmost pins of the header, GND is shorted to EN and the TPS7A53A-Q1 is
disabled.
When driving the EN terminal with an offboard supply or signal generator, the applied voltage must be kept
between 0 V and V
IN
.
www.ti.com Introduction
SBVU078 – NOVEMBER 2022
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