First Initialization
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3
First Initialization
3.1
I/O Polarity/Muxing Configuration
Program DEVCTRL2_REG.SLEEPSIG_POL according to the GPIO level setting on the processor. This
can be set to active low or active high for SLEEP transitions. Software configuration allows specific power
resources to enter a low consumption state.
Set DEVCTRL_REG.DEV_SLP = 1 to allow SLEEP transitions when requested.
Update the GPIO0 configuration (GPIO0_REG) based on your needs.
3.2
Define Wake-Up/Interrupt Event (SLEEP or OFF)
Select the appropriate bits in the INT_MSK_REG and INT_MSK2_REG registers to activate an interrupt to
the processor on the INT1 line.
3.3
Backup Battery Configuration
If a backup battery is used, enable backup battery charging by setting the BBCH_REG.BBCHEN bit to 1.
The maximum charge voltage can be set based on the backup battery specifications by using the BBSEL
bits.
3.4
DCDC and Voltage Scaling Resource Configuration
If the SmarReflex interface is not used for viltage scaling (power saving), these pins can be used to
control the power resources.
Configure two operating voltages for DCDC1 and DCDC2
•
VDDx_OP_REG.SEL= Roof voltage (ENx ball high)
•
VDDx_SR_REG.SEL = Floor voltage (ENx ball low)
Assign control for DCDC1 to SCLSR_EN1 and DCDC2 to SCLSR_EN2:
•
Set EN1_SMPS_ASS_REG.VDD1_EN1 = 1
•
Set EN2_SMPS_ASS_REG.VDD2_EN1 = 2
•
Set SLEEP_KEEP_RES_ON_REG.VDD1_KEEPON = 1 (allow low-power mode)
•
Set SLEEP_KEEP_RES_ON_REG.VDD2_KEEPON = 1 (allow low-power mode)
3.5
Sleep Platform Configuration
Configure the state of the LDOs when the SLEEP signal is used (by default all resources go into SLEEP
state; in SLEEP state the LDO voltage is maintained but transient and load capability are reduced).
Resources that must provide full load capability must be set in the SLEEP_KEEP_LDO_ON_REG register.
Resources that can be set off in SLEEP state to optimize power consumption must be set in the
SLEEP_SET_LDO_OFF_REG register.
10
TPS65910Ax User's Guide For AM335x Processors
SWCU093C – August 2011 – Revised May 2013
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