Texas Instruments TPS65235-1, Руководство пользователя

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J2
VIN
Test Point A J7
EN Control
J6
ADDR Control
J1
VOUT
J4
EXTM Control
J3
SCL/I2C Power
P1
I2C Interface to PC
J5
VCTRL Control
Bench Test Setup Conditions
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6 SLVUAZ0 – November 2016
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Evaluation Module for the TPS65235-1 LNB Voltage Regulator With I
2
C
Interface for DiSEqC2.x Application
4 Bench Test Setup Conditions
4.1 Headers Description and Jumper Placement
Figure 5 shows the header descriptions and jumper placement.
Figure 5. Headers Description and Jumper Placement
Test points:
A: LX for Boost
Notes:
• At non-I
2
C mode, P1 should be floating, J5 and J3 are used to set the output, refer to Table 3 .
• At I
2
C mode, P1 is connected to the PC through the USB-TO-GPIO box, which makes the SCL signal
to be high. J5 can be used to set the default output when powered on, refer to Table 3 .
• P1 and J3 cannot be connected at the same time.
Table 1 lists the I/O connections and Table 2 lists the EVM jumpers and switches.