Texas Instruments TPS62933, Руководство пользователя

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5 Board Layout
This section provides a description of the TPS62933EVM, board layout, and layer illustrations.
5.1 Layout
The board layout for the TPS62933EVM is shown in Figure 5-1 , Figure 5-2 , and Figure 5-3 . The top layer
contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins
of the TPS62933 and a large area filled with ground. Most of the signal traces are also located on the top side.
The input decoupling capacitors, C6, C7, C8, and C9 are located as close to the IC as possible. The input and
output connectors, test points, and all of the components are located on the top side. The bottom layer is a
ground plane along with the switching node copper fill, signal ground copper fill and the feed back trace from the
point of regulation to the top of the resistor divider network. Both the top layer and bottom layer use 2 oz copper
thickness.
Figure 5-4 and Figure 5-5 are the TPS62933EVM board top view and bottom view, respectively.
Figure 5-1. TPS62933EVM Top Assembly
Board Layout www.ti.com
10 TPS62933EVM-129 3-A Regulator Evaluation Module SLUUCH1 – JUNE 2021
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