1 Introduction
The TPS62866 is a synchronous, step-down converter in a 1.05- x 1.78- x 0.5-mm wafer chip-scale package
(WCSP).
1.1 Performance Specification
provides a summary of the TPS62866EVM-051 performance specifications.
Table 1-1. Performance Specification Summary
SPECIFICATION
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input voltage
2.4
5
5.5
V
Output voltage setpoint
0.9
V
Output current
0
6000
mA
1.2 Modifications
The EVM can support variance of the whole IC family. Additional input and output capacitors can be added.
2 Setup
This section describes how to properly use the TPS62866EVM-051.
2.1 Input/Output Connector Descriptions
J1, Pin 1 and 2 – VIN
Positive input connection from the input supply for the EVM
J1, Pin 3 and 4 – S+/S-
Input voltage sense connections. Measure the input voltage at this point.
J1, Pin 5 and 6 – GND
Input return connection from the input supply for the EVM
J2, Pin 1 and 2 – VOUT
Output voltage connection
J2, Pin 3 and 4 – S+/S-
Output voltage sense connections. Measure the output voltage at this point.
J2, Pin 5 and 6 – GND
Output return connection
J3, Pin 5 – VBUS
The VBUS pin of this header is used to bias the SCL and SDA nodes of I²C interface
via a resistor.
J3, Pin 6 – GND
The GND pin of this header is used to connect the grounds of the IC and the I²C
interface.
J3, Pin 9 – SCL
The pin of this header should be connected to the SCL of the I²C interface.
J3, Pin 10 – SDA
The pin of this header should be connected to the SDA of the I²C interface.
JP1 – VID/PG
VID/ PG pin jumper. Always place the jumper across VID/ PG and LOW pins before
start-up. This sets the output voltage and device address. After startup, VOUT reflects
the value set on V
OUT
Register 1 if the jumper is placed across VID/ PG and LOW
pins. VOUT follows the value set on V
OUT
Register 2 if the jumper is placed across
VID/ PG and HIGH pins.
JP2 – EN
EN pin input jumper. Place the jumper across ON and EN to turn on the IC. Place the
jumper across OFF and EN to turn off the IC.
2.2 Setup
To operate the EVM, set jumpers JP1 and JP2 to the desired position per
to J1 and connect the load to J2.
Introduction
2
TPS62866EVM-051 Evaluation Module
SLUUC21A – JULY 2019 – REVISED JULY 2021
Copyright © 2021 Texas Instruments Incorporated