Texas Instruments TPS563211, Руководство пользователя

Страница: 5 / 15

5 Board Layout
This section provides a description of the TPS563211EVM, board layout, and layer illustrations.
5.1 Layout
The board layout for the TPS563211EVM is shown in Figure 5-1 , Figure 5-2 , and Figure 5-3 . The top layer
contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins of
the TPS563211 and a large area filled with ground. Most of the signal traces are also located on the top side.
The input decoupling capacitors, C1, C2, and C3 are located as close to the IC as possible. The input and output
connectors, test points, and all of the components are located on the top side. The bottom layer is a ground
plane along with the switching node copper fill, signal ground copper fill and the feed back trace from the point of
regulation to the top of the resistor divider network. Both the top layer and bottom layer use 2-oz copper
thickness.
Figure 5-1. TPS563211EVM Top Assembly
www.ti.com Board Layout
SLUUCC6 – SEPTEMBER 2020
Submit Document Feedback
TPS563211 18-V Input, 3-A Output, 600-kHz, Synchronous Buck Converter
SOT583 Evaluation Module
5
Copyright © 2020 Texas Instruments Incorporated