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3 Test Setup and Results
This section describes how to properly connect, set up, and use the TPS543320EVM evaluation module.
The section also includes test results typical for the evaluation module and covers efficiency, output voltage
regulation, load transients, loop response, output ripple, input ripple, start-up, and current limit modes.
Measurements are taken with the following conditions unless otherwise noted.
• 12-V input
• Room temperature (20°C to 25°C)
• U2 with the default setting output voltage of 1 V, switching frequency of 1000 kHz, and maximum current limit
setting
• With the other converter disabled
3.1 Input/Output Connections
The TPS543320EVM is provided with input connectors, output connectors, and test points as shown in Table 3-1
and Table 3-2 .
To support the minimum input voltage with the full rated load on both outputs with the default EVM, a power
supply capable of supplying greater than 3 A must be connected to J8 through a pair of 20-AWG wires or better.
Banana jacks J5 and J9 provide an alternative connection to input power supply.
For U1, the load must be connected to J2 and for U2, the load must be connected to J7. A pair of 20-AWG wires
or better must be used for each connection. With the maximum current limit setting, the maximum load current
capability is near 5 A before the TPS543320 goes into current limit. Wire lengths must be minimized to reduce
losses in the wires.
Test point TP11 provides a place to monitor the V
IN
input voltage with TP19 providing a convenient ground
reference. TP2 is used to monitor the output voltage of U1 with TP5 as the ground reference. TP15 is used to
monitor the output voltage of U2 with TP17 as the ground reference.
If modifications are made to the TPS543320EVM, the input current may change. The input power supply and
wires connecting the EVM to the power supply must be rated for the input current.
Note
For the FSEL pin of the TPS543320 to detect and set the correct switching frequency, the pin must
either detect the resistor to ground or an external clock must applied to the pin before enabling the
regulator. If starting up without an external clock, to properly detect the FSEL resistor value connected
to ground, the buffers on the EVM need to be in high impedance mode. The shunts on J15 and J16
must be removed to put the buffers in high impedance mode for startup without an external clock.
Test Setup and Results www.ti.com
8 TPS543320 SWIFT™ Step-Down Converter Evaluation Module User's Guide SLVUC07A – DECEMBER 2020 – REVISED MAY 2021
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