manualshive.com logo in svg

Texas Instruments TPD1E04U04, Руководство пользователя


Поделиться
Скачать
background image

Board Layout

www.ti.com

6

SLVUAN8 – April 2016

Submit Documentation Feedback

Copyright © 2016, Texas Instruments Incorporated

TPD1E04U04 Evaluation Module

4

Board Layout

This section provides the TPD1E04U04EVM board layout. TPD1E04U04EVM is a 4-layer board of
FR408HR at 0.062 inch thickness. Layers 2, 3, and 4 are ground planes and not shown here.

Figure 3. TPD1E04U04EVM Top Layer and Silkscreen

5

Schematics

Figure 4. TPD1E04U04EVM Schematic

Содержание TPD1E04U04

Страница 1: ...lysis This user s guide includes setup instructions schematic diagrams a bill of materials and printed circuit board layout drawings for the evaluation module Contents 1 Introduction 2 2 Definitions 2 3 Setup 3 3 1 IEC 61000 4 2 ESD Rating Tests 3 3 2 Scattering Parameters 4 3 3 8 kV ESD Clamping Waveforms 4 4 Board Layout 6 5 Schematics 6 6 Bill of Materials 7 List of Figures 1 Ideal Contact Disc...

Страница 2: ...o as not to damage the oscilloscope A proper procedure is outlined in Section 3 3 1 2 Definitions Contact Discharge a method of testing in which the electrode of the ESD simulator is held in contact with the device under test DUT Air Discharge a method of testing in which the charged electrode of the ESD simulator approaches the DUT and a spark to the DUT actuates the discharge ESD Simulator a dev...

Страница 3: ...0 4 2 ESD Rating Tests TPD1E04U04DPY D1 D5 can be used for destructive electrostatic discharge ESD pass or fail ESD strikes Specifically they can be used for both IEC 61000 4 2 air and contact discharge tests The procedure in Section 3 1 1 ensures proper testing setup and method for both discharge tests Each IO has a Test Pad TP1 TP5 directly connected to it for striking ESD 3 1 1 Test Method and ...

Страница 4: ...the ESD protection diode shifts 0 1 V or leakage current increases by a factor of ten then the device is permanently damaged by ESD 3 2 Scattering Parameters A TPD1E04U04 D6 is configured with 2 SMA J1 and J2 connectors to allow 2 port analysis with a vector network analyzer Connect Port 1 to J1 and Port 2 to J2 This configuration allows for the following terminology in 2 port analysis S11 Return ...

Страница 5: ... the oscilloscope attenuation of the measured signal is required Here is a procedure for testing D3 1 Ground the EVM using the banana connector J3 2 Attach two 10X attenuators in series to the oscilloscope channel being used 3 Attach the 50 Ω shielded SMA cable between J2 and the attenuators 4 Set the scope attenuation factor to 100X 5 Set the oscilloscope to trigger on a positive edge for ESD and...

Страница 6: ...ated TPD1E04U04 Evaluation Module 4 Board Layout This section provides the TPD1E04U04EVM board layout TPD1E04U04EVM is a 4 layer board of FR408HR at 0 062 inch thickness Layers 2 3 and 4 are ground planes and not shown here Figure 3 TPD1E04U04EVM Top Layer and Silkscreen 5 Schematics Figure 4 TPD1E04U04EVM Schematic ...

Страница 7: ...Table 3 Bill of Materials Count RefDes Description Package Reference Part Number MFR 6 D1 D2 D3 D4 D5 D6 1 Channel ESD Protection Device for Super Speed up to 6 Gbps Interface DPY0002A DPY0002A TPD1E04U04DPY Texas Instruments 2 J1 J2 Connector TH End launch SMA 50 Ω Connector TH End launch SMA 142 0761 881 Johnson 1 J3 Standard Banana Jack Insulated Black 6092 6092 Keystone ...

Страница 8: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

Отзывы:

Нет отзывов

Похожие инструкции для TPD1E04U04

Бренды по названию

Популярные бренды

Загрузить еще бренды