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Usage Notes and Known Design Exceptions to Functional Specifications

15

SPRZ412K – December 2013 – Revised February 2020

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Copyright © 2013–2020, Texas Instruments Incorporated

TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0

Advisory

ADC: ADC Sparkle Codes

Revision(s) Affected

0, A

Details

The ADC may give conversion results with large random errors (sparkle codes). When
present, this is typically observed as a large jump in the conversion result for a single
code while sampling a continuously varying waveform.

Workaround(s)

Bad codes can be reduced by writing the value 0x7000 to memory locations
0x0000 743F, 0x0000 74BF, 0x0000 753F, and 0x0000 75BF.

This workaround is valid only on the revisions affected.

Advisory

ADC: ADC Linearity Performance

Revision(s) Affected

0

Details

INL/DNL performance does not meet data sheet specifications. For 16-bit mode, typical
performance is: INL = ±12 LSBs, DNL = [+1.5,-1] LSBs. Missing codes are present every
512 codes, in sets of up to 16 missing codes in a row. For 12-bit mode, typical
performance is: INL = ±4 LSB, DNL = [+1, -1] LSBs. Missing codes are present every
128 codes, in sets of up to 4 missing codes in a row.

Workaround(s)

None

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Содержание TMS320F2837 D Series

Страница 1: ...ion devices and tools with TMS for devices and TMDS for tools TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow TMDX Deve...

Страница 2: ... www ti com 2 SPRZ412K December 2013 Revised February 2020 Submit Documentation Feedback Copyright 2013 2020 Texas Instruments Incorporated TMS320F2837xD Dual Core MCUs Silicon Revisions C B A 0 3 Device Markings Figure 1 provides an example of the 2837xD device markings and defines each of the markings The device revision can be determined by the symbols marked on the top of the package as shown ...

Страница 3: ...anual CPU Interrupt Mask Clear Revision s Affected 0 A B C Certain code sequences used for nested interrupts allow the CPU and PIE to enter an inconsistent state that can trigger an unwanted interrupt The conditions required to enter this state are 1 A PIEACK clear is followed immediately by a global interrupt enable EINT or asm CLRC INTM 2 A nested interrupt clears one or more PIEIER bits for its...

Страница 4: ...n to ensure a clean and noise free signal that meets the SDFM timing requirements Precautions such as series termination for ringing due to any impedance mismatch of the clock driver and spacing of traces from other high frequency signals are recommended SDFM GPIO Qualification 3 sample Mode It is highly recommended that the SDFM GPIO qualification mode be used in noisy conditions This mode provid...

Страница 5: ... Yes Yes Yes Yes Flash Minimum Programming Word Size Yes Yes Yes Yes Flash Reset of CPU2 While it has Pump Ownership Can Cause Erroneous Flash Reads From CPU1 Yes Yes ePIE Spurious VCU Interrupt ePIE 12 6 Can Occur When First Enabled Yes Yes Yes eQEP Position Counter Incorrectly Reset on Direction Change During Index Yes Yes Yes Yes eQEP eQEP Inputs in GPIO Asynchronous Mode Yes Yes Yes Yes PLL Ma...

Страница 6: ...nces Different Flash Sector Changed From Sector A to Sector B Yes Yes McBSP McBSP Transmit in SPI Slave Mode Yes Yes Crystal Maximum Equivalent Series Resistance ESR Values are Reduced Yes Yes Table 4 Table of Contents for Advisories Title Page Advisory Analog Bandgap References 8 Advisory Analog Trim of Some TMX Devices 9 Advisory ADC ADC Post Processing Block Limit Compare 10 Advisory ADC Interr...

Страница 7: ...structions 29 Advisory Memory Prefetching Beyond Valid Memory 32 Advisory INTOSC VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift 32 Advisory Low Power Modes Power Down Flash or Maintain Minimum Device Activity 33 Advisory I2C SDA and SCL Open Drain Output Buffer Issue 34 Advisory ePWM An ePWM Glitch can Occur if a Trip Remains Active at the End of the Blanking Window 36 Advisory ePWM e...

Страница 8: ...nt modules are enabled An active bandgap reference will power down if all dependent modules are disabled For example bandgap B BGB is powered down unless one or more of the following register bits are set AdcbRegs ADCCTL1 bit ADCPWDNZ DaccRegs DACOUTEN bit DACOUTEN Cmpss3Regs COMPCTL bit COMPDACE Cmpss4Regs COMPCTL bit COMPDACE The CMPSS and GPDAC power up time specification in the TMS320F2837xD D...

Страница 9: ...graded frequency accuracy and temperature drift of the internal oscillators AnalogSubsysRegs INTOSC2TRIM Buffered DAC offset DacaRegs DACTRIM Degraded offset error specification of the buffered DAC No workaround available DacbRegs DACTRIM DaccRegs DACTRIM Workaround s The following workarounds can be used for improved performance though it still may not meet data sheet specifications To determine ...

Страница 10: ...then interrupts will stop when the ADCINTFLG is set and no additional ADC interrupts will occur When an ADC interrupt occurs simultaneously with a software write of the ADCINTFLGCLR register the ADCINTFLG will unexpectedly remain set blocking future ADC interrupts Workaround s 1 Use Continue to Interrupt Mode to prevent the ADCINTFLG from blocking additional ADC interrupts ADCINTSEL1N2 INT1CONT 1 ...

Страница 11: ...T and tINT LATE columns in the ADC Timings tables of the TMS320F2837xD Dual Core Microcontrollers Data Manual The DMA can read the ADCRESULT value as soon as 3 cycles after the ADCINT trigger is set As a result the DMA could read a prior ADCRESULT value when the user expects the latest result if all of the following are true The ADC is in late interrupt mode The ADC operates in a mode where tINT L...

Страница 12: ...owing configurations are used The S H duration is at least 320 ns ADCCLK is 40 MHz or less ADCCLK prescale is a whole number 1 0 2 0 3 0 4 0 5 0 6 0 7 0 or 8 0 The value of 0x7000 is written to memory locations 0x0000 743F 0x0000 74BF 0x0000 753F and 0x0000 75BF writing this value is only valid when the ADCCLK prescale is a whole number Advisory ADC ADC PPB Event Trigger ADCxEVT to ePWM Digital Co...

Страница 13: ...fected when subsequent conversions switch between channel groups the S H duration should be chosen to account for the additional capacitance Advisory ADC Functionality of VREFLO Pins Revision s Affected 0 A Details The VREFLO pins on Revision 0 and Revision A silicon are not connected VREFLO functionality for all ADCs is provided by an internal connection to VSSA on these revisions This may result...

Страница 14: ...onal connection occurs If the previously converted channel and the currently converting channel are both odd numbered channels or both even numbered channels for example A6 and A14 then the two channels will be briefly connected If the previously converted channel and the currently converting channel are not both odd numbered channels or not both even numbered channels for example A6 and A15 then ...

Страница 15: ...gle code while sampling a continuously varying waveform Workaround s Bad codes can be reduced by writing the value 0x7000 to memory locations 0x0000 743F 0x0000 74BF 0x0000 753F and 0x0000 75BF This workaround is valid only on the revisions affected Advisory ADC ADC Linearity Performance Revision s Affected 0 Details INL DNL performance does not meet data sheet specifications For 16 bit mode typic...

Страница 16: ...e within an acceptable range and XRS is high Workaround s Disregard XRS activity on the board prior to supplies reaching recommended operating conditions Advisory USB USB DMA Event Triggers are not Supported Revision s Affected 0 A B C Details The USB module generates inadvertent extra DMA requests causing the FIFO to overflow on IN endpoints or underflow on OUT endpoints This causes invalid IN DA...

Страница 17: ...hat the default value of the threshold bit field is 0 Advisory Flash Minimum Programming Word Size Revision s Affected 0 A B C Details The Main Array flash programming must be aligned to 64 bit address boundaries and each 64 bit word may only be programmed once per write erase cycle Applications using Fapi_issueProgrammingCommand in Fapi_AutoEccGeneration or Fapi_DataAndEcc modes are implicitly pe...

Страница 18: ...incorrect program execution or an unspecified error in the application This erratum does not apply if the CPU2 Subsystem never writes to the PUMPREQUEST register to take ownership of the flash pump semaphore Workaround s CPU1 must not access flash while CPU2 holds the flash pump semaphore ownership The following steps describe how this can be achieved 1 At application start up CPU2 reads the PUMPR...

Страница 19: ...incorrectly sets the VCU VSTATUS DIVE error bit and subsequently PIEIFR12 INTx6 when the CPU is released from reset When the VCU interrupt enable PIEIER12 INTx6 is enabled for the first time by the application a spurious interrupt can occur due to the erroneous pending interrupt Workaround s Before enabling VCU interrupt 12 6 execute the following instructions to avoid the spurious interrupt Clear...

Страница 20: ...le the index pulse is active the module would still continue to look for the relative quadrature transition for performing the position counter reset This results in an unexpected change in the position counter value The next index event without a simultaneous direction change will reset the counter properly and work as expected Workaround s Do not use the PCRM 0 configuration if the direction cha...

Страница 21: ...eans disabling the PLL starting the PLL locking and waiting for the LOCKS bit to set After the final sequence the clock source is switched to use the PLL output as normal The Watchdog timer can be used to detect that the condition has occurred because it is not clocked by the PLL output The Watchdog should be enabled before selecting the PLL as the clock source and configured to reset the device I...

Страница 22: ...t will need to implement any retry attempts at the system level Advisory PLL Power Down and Bypass May Take up to 120 SYSCLK Cycles to be Effective Revision s Affected 0 A B C Details When the PLL is powered down that is SYPLLCTL1 PLLEN 0 or bypassed that is SYSPLLCTL1 PLLCLKEN 0 there is a necessary period of clock synchronization before the PLL bypass completes During this time if PLLSYSCLKDIV o...

Страница 23: ...e it is possible to get one spurious data acknowledge event AFx before the data filter settles to give correct digital data Subsequent data acknowledge events AFx DMA events occur correctly as per data filter configuration Workaround s Do the following 1 Configure and enable the SDFM data filter 2 Delay for at least latency of data filter 5 SD Cx clock cycles 3 Enable SDFM data acknowledge interru...

Страница 24: ...l Trigger Spurious Comparator Events Revision s Affected 0 A B C Details When SDFM comparator settings such as filter type lower upper threshold or comparator OSR COSR settings are dynamically changed during run time spurious comparator events will be triggered The spurious comparator event will trigger a corresponding CPU interrupt CLA task ePWM X BAR events and GPIO output X BAR events if config...

Страница 25: ...hen SDFM data settings such as filter type or DOSR settings are dynamically changed during run time spurious data filter ready events will be triggered The spurious data ready event will trigger a corresponding CPU interrupt CLA task and DMA trigger if configured appropriately Workaround s When SDFM data filter settings need to be changed dynamically follow the procedure below to ensure spurious d...

Страница 26: ...2p instruction destination then the read may be of the value of the FPU register before the 2p instruction completes This occurs because the 2p instructions rely on data forwarding of the result during the E3 phase of the pipeline If a pipeline stall happens to occur in the E3 phase the result does not get forwarded in time for the read instruction The 2p instructions impacted by this advisory are...

Страница 27: ...MS320F2837xD Dual Core MCUs Silicon Revisions C B A 0 Figure 5 shows the pipeline diagram of the issue if there is a stall in the E3 slot of the instruction I1 Figure 5 Pipeline Diagram of the Issue if There is a Stall in the E3 Slot of the Instruction I1 Workaround s Treat MPYF32 ADDF32 SUBF32 and MACF32 in this scenario as 3p cycle instructions Three NOPs or non conflicting instructions must be ...

Страница 28: ...ere is no change due to the stall in the previous cycle I5 I4 I3 I2 I1 moves out of E3 and I5 moves to R2 R6H has the result of R5H R0H and is read by I5 There is no need to forward the result in this case I5 I4 I3 I3 I3 I2 I1 Comments FPU pipeline I1 I1 Usage Notes and Known Design Exceptions to Functional Specifications www ti com 28 SPRZ412K December 2013 Revised February 2020 Submit Documentat...

Страница 29: ...INVF32 in assembly only code Do not rely on the LUF and LVF flags to catch underflow overflow conditions resulting from the EINVF32 and EISQRTF32 instructions Instead check the operands for the following conditions in code before using each instruction EINVF32 Divide by 0 EISQRTF32 Divide by 0 Divide by a negative input Disregard the contents of the LUF and LVF flags by saving the flags to the sta...

Страница 30: ...n MOVL XAR3 _flag_LVFLUF_set Wait for operation to complete MOV32 XAR3 0 STF save STF to _flag_LVFLUF_set AND XAR3 0 0x3 mask everything but LUF LVF Clear Latched overflow underflow flag SETFLG LUF 0 LVF 0 Re enable PIEIER12 7 8 i e re enable the LUF LVF interrupts OR _PieCtrlRegs PIEIER12 all 0x00C0 MOV32 STF SP Restore previous status flags In the ISR __interrupt void fpu32_luf_lvf_isr void Chec...

Страница 31: ...ion boundaries Thus although the sqrt routine in the library may cause LVF LUF to be set there is no assurance in the CGT that the user can read these bits after sqrt returns Although the compiler does provide the __eisqrtf and __einvf32 intrinsics it does not provide an intrinsic to read the LVF LUF bits or the STF register Thus the user has no way to access these bits from C code The use of inli...

Страница 32: ... memory otherwise it generates a Flash ECC uncorrectable error Table 6 Memories Impacted by Advisory MEMORY TYPE ADDRESSES IMPACTED F28378D F28377D F28375D F28376D F28374D M1 0x0000 07F8 0x0000 07FF Yes Yes GS11 0x0001 7FF8 0x0001 7FFF No Yes GS15 0x0001 BFF8 0x0001 BFFF Yes N A Flash 0x000B FFF0 0x000B FFFF Yes N A Advisory INTOSC VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift Revisi...

Страница 33: ...ound 1 Power down the flash before entering HALT STANDBY IDLE or other low activity device conditions This will disable the internal current path This workaround must be executed from RAM CPU 1 EALLOW seize the pump semaphore while IpcRegs PUMPREQUEST bit SEM 0x2 IpcRegs PUMPREQUEST all IPC_PUMP_KEY 0x2 Flash0CtrlRegs FBFALLBACK bit BNKPWR0 0 asm RPT 8 NOP power down pump Flash0CtrlRegs FPAC1 bit ...

Страница 34: ...ries termination resistors near the SCL and SDA terminals to attenuate transmission line reflections This issue may also cause the SDA output to be in contention with the slave SDA output for the duration of the unexpected high level pulse when the slave begins its ACK cycle This occurs because the slave may already be driving SDA low before the unexpected high level pulse occurs The glitch that o...

Страница 35: ... recommendations The I2C signal level and respective VDDIO power supply voltage is shown in the first column Two resistor value combination options are provided for each voltage One option supports a maximum high level input current of 200 uA to all attached I2C devices while the other option supports a maximum high level input current of 100 uA to all attached I2C devices Table 7 Recommended Valu...

Страница 36: ...tions which would be false trips to the system If an ePWM trip event remains active for less than three ePWM clocks after the end of the blanking window cycles there can be an undesired glitch at the ePWM output Figure 8 illustrates the time period which could result in an undesired ePWM output Figure 8 Undesired Trip Event and Blanking Window Expiration Figure 9 illustrates the two potential ePWM...

Страница 37: ...ock ratio between SYSCLK and the clock selected by OSCCLKSRCSEL and may not occur every time If this issue is encountered while using the debugger then after hitting pause the program counter will be at the Boot ROM reset vector Implementing the workaround will avoid this condition for any SYSCLK to OSCCLK ratio Workaround s Add a software delay of 300 SYSCLK cycles using an NOP instruction after ...

Страница 38: ...ing the latch For instances where a large LATENCY value produces intolerable delays the filter FIFO may be flushed by reinitializing the Digital Filter via CTRIPxFILCTL If COMPxLATCH is cleared by PWMSYNC the user application should be designed such that the comparator trip condition is cleared at least LATENCY cycles before PWMSYNC is generated Advisory CMPSS Ramp Generator May Not Start Under Ce...

Страница 39: ...tress to both devices and results in a brief intermediate voltage level on the signal This intermediate voltage level may be incorrectly interpreted as a high level if there is not sufficient logic filtering present in the receiver logic to filter this brief pulse Workaround s If contention is a concern do not use the open drain functionality of the GPIOs instead emulate open drain mode in softwar...

Страница 40: ...e speed of signals switching on these pins with fast switching transients more likely to induce the condition The condition has only been observed when the signal at the device pin has a rise time or fall time faster than 2 ns measured 10 to 90 of VDDIO The condition will resolve upon toggle of the IO at a lower temperature Workaround s Try one of these two options Option 1 Avoid the use of these ...

Страница 41: ...he FIFO Buffer Revision s Affected 0 A B C Details In DCAN FIFO mode received messages with the same arbitration and mask IDs are supposed to be placed in the FIFO in the order in which they are received The CPU then retrieves the received messages from the FIFO via the IF1 IF2 interface registers Some messages may be placed in the FIFO out of the order in which they were received If the order of ...

Страница 42: ...ROM Using CPU1 Wait Boot or CPU2 Idle Mode Revision s Affected 0 A B C Details The PIE Initialize Vector Table function that is part of the CPU1 and CPU2 ROMs writes beyond the PIE vector table addresses up to address 0x1080 If the DMA clock is enabled before a debugger reset and CPU1 goes to wait boot or CPU2 goes to idle mode then some DMA registers will be overwritten during the ROM PIE vector ...

Страница 43: ...ult in the clearing of other bits in the HRCNFG register Do not read the even numbered HRPWM module registers or use the contents in any software Only modify the entire register with HRCNFG all when writing to the even numbered HRPWM module registers Advisory SYSBIOS in ROM References Different Flash Sector Changed From Sector A to Sector B Revision s Affected 0 A Details This advisory applies onl...

Страница 44: ...s are reduced For the revisions affected the data in Table 8 supersedes the data given in the Crystal Equivalent Series Resistance ESR Requirements table in the TMS320F2837xD Dual Core Microcontrollers Data Manual The differences between the two tables are highlighted in Table 8 1 Crystal shunt capacitance C0 should be less than or equal to 7 pF Table 8 Crystal Equivalent Series Resistance ESR Req...

Страница 45: ...7xD Dual Core MCUs Silicon Revisions C B A 0 5 Documentation Support For device specific data sheets and related documentation visit the TI web site at http www ti com For more information regarding the TMS320F2837xD devices see the following documents TMS320F2837xD Dual Core Microcontrollers Data Manual TMS320F2837xD Dual Core Microcontrollers Technical Reference Manual ...

Страница 46: ...uary 2020 Submit Documentation Feedback Copyright 2013 2020 Texas Instruments Incorporated TMS320F2837xD Dual Core MCUs Silicon Revisions C B A 0 Trademarks PowerPAD TMS320 are trademarks of Texas Instruments All other trademarks are the property of their respective owners ...

Страница 47: ... Mode is not Set advisory 10 Section 4 2 Added ADC DMA Read of Stale Result advisory 11 Section 4 2 Added PLL Power Down and Bypass May Take up to 120 SYSCLK Cycles to be Effective advisory 22 Section 4 2 Updated SDFM Dynamically Changing Threshold Settings LLT HLT Filter Type or COSR Settings Will Trigger Spurious Comparator Events advisory 24 Section 4 2 Updated SDFM Dynamically Changing Data Fi...

Страница 48: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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