1.2
Industry Compliance Statement
2
Peripheral Architecture
2.1
Clock Control
2.2
Signal Descriptions
2.3
Functional Operation
2.3.1
One-Shot Mode Operation
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Peripheral Architecture
The ADC interface does not conform to any recognized industry standards.
The ADC interface is driven by the auxiliary clock of the PLL controller. The frequency of the auxiliary
clock is equal to the input reference clock of the PLL controller, and therefore is not affected by the
multiplier and divider values of the PLL controller. For more information on device clocking, refer to the
TMS320DM365 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide
(
SPRUFG5
).
The ADC interface receives analog inputs on six separate pins: ADC_CH [5:0]. Refer to the
TMS320DM365 Digital Media System-on-Chip Data Manual
(
SPRS457
) for more information on these
pins.
The ADC interface can operate in either one-shot mode or free-run mode. In both modes, the ADC
peripheral has a Comparison A/D Lower data register (CMPLDAT) and a Comparison A/D Upper data
register (CMPUDAT) to specify, respectively, the lower and upper data for comparison. The analog input
channel to be used for scan conversion can be configured using the CHSEL registers and on the
CMPTGT register, set the analog input data to be the target of comparator. For one-shot mode operation,
see
Section 2.3.1
; for Free-Run mode operation, see
Section 2.3.2
.
In one-shot mode operation, the ADC interface does not run continuously and A/D conversion terminates
when scanning is completed.
For one-shot mode operation, the ADC interface should first be configured for scan mode (SCNMD) and
comparator mode (CMPMD) in ADC interface control register (ADCTL), along with other configuration
options. The ADC interface sets the BUSY bit in ADCTL once it is started by writing a 1 to the START bit
in the ADCTL register
Once started, the ADC interface genertaes the output after A/D conversion time. A/D conversion time is
obtained by Analog switch setup time + ADC setup time + A/D conversion time.
•
Analog switch setup time = Peripheral CLK period * (SET_DIV[5:0] + 3)*2
•
ADC setup time = Peripheral CLK period * (SET_DIV[15:0] + 1)*2
•
A/D conversion time = Peripheral CLK period* (SET_DIV[5:0] + 1)*24
When the A/D scan conversion is finished for all channels, the peripheral sends an interrupt to the system
(if the interrupt is enabled in ADCTL register). The START bit will cleared automatically when A/D
conversion in One-Shot mode terminates. The ADC interface then becomes inactive until the START bit is
written a 1 again.
The ADC Interface is stopped during one-shot mode operation by changing the START bit to 0 in ADCTL.
After START bit turns to '0', it will be stop at the completion of current sample conversion. If user change
configuration, then user need to wait at least a time which defined by SETDIV register after writing '0' into
START bit.
SPRUFI7 – March 2009
Analog to Digital Converter (ADC) Interface
9
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