Parallel Operations
3-13
TMS320C62x/C67x Fixed-Point Instruction Set
3.5
Parallel Operations
Instructions are always fetched eight at a time. This constitutes a
fetch packet.
The basic format of a fetch packet is shown in Figure 3–2. Fetch packets are
aligned on 256-bit (8-word) boundaries.
Figure 3–2. Basic Format of a Fetch Packet
p
p
p
p
p
p
p
p
Instruction
A
000002
Instruction
B
001002
Instruction
C
010002
Instruction
D
011002
Instruction
E
100002
Instruction
F
101002
Instruction
G
110002
Instruction
H
111002
LSBs of
the byte
address
31
0 31
0 31
0 31
0 31
0 31
0 31
0 31
0
The execution of the individual instructions is partially controlled by a bit in
each instruction, the
p-bit. The p -bit (bit 0) determines whether the instruction
executes in parallel with another instruction. The
p-bits are scanned from left
to right (lower to higher address). If the
p -bit of instruction i is 1, then instruction
i + 1 is to be executed in parallel with (in the the same cycle as) instruction i.
If the
p-bit of instruction i is 0, then instruction i + 1 is executed in the cycle after
instruction
i. All instructions executing in parallel constitute an execute packet.
An execute packet can contain up to eight instructions. Each instruction in an
execute packet must use a different functional unit.
An execute packet cannot cross an 8-word boundary. Therefore, the last
p-bit
in a fetch packet is always set to 0, and each fetch packet starts a new execute
packet. There are three types of
p -bit patterns for fetch packets. These three
p -bit patterns result in the following execution sequences for the eight instruc-
tions:
-
Fully serial
-
Fully parallel
-
Partially serial
Example 3–1 through Example 3–3 illustrate the conversion of a
p-bit se-
quence into a cycle-by-cycle execution stream of instructions.
