Overview of Thread Scheduling
4-10
Figure 4-2.
Preemption Scenario
In Figure 4-2, the low priority software interrupt is asynchronously preempted
by the hardware interrupts. The first ISR posts a higher-priority software
interrupt, which is executed after both hardware interrupt routines finish
executing.
Содержание TMS320 Series
Страница 1: ...TMS320 DSP BIOS v5 40 User s Guide Literature Number SPRU423G April 2009 ...
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