Table 10-3. GPIO Drive Strength Options
Drive (mA)
GPIODR2R (2mA)
GPIODR4R
(+2mA)
GPIODR8R
(+4mA)
GPIODR12R
(+4mA)
EDMn
(GPIOPC)
EDE
(GPIOPP)
2
1
0
0
N/A
0x0
X
4
0
1
0
8
0
0
1
2
N/A
0
0
N/A
0x1
1
4
N/A
1
0
6
N/A
0
1
8
N/A
1
1
2
N/A
0
0
0
0x3
1
4
N/A
1
0
0
6
N/A
0
1
0
8
N/A
1
1
0
10
N/A
0
1
1
12
N/A
1
1
1
N/A
N/A
N/A
0
1
N/A
N/A
N/A
N/A
N/A
0x2
1
10.3.6
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the
GPIOPeriphID0
-
GPIOPeriphID7
registers as
well as the
GPIOPCellID0
-
GPIOPCellID3
registers.
10.4
Initialization and Configuration
To configure the GPIO pins of a particular port, follow these steps:
1.
Enable the clock to the port by setting the appropriate bits in the
RCGCGPIO
register (see
page 382). In addition, the
SCGCGPIO
and
DCGCGPIO
registers can be programmed in the
same manner to enable clocking in Sleep and Deep-Sleep modes.
2.
Set the direction of the GPIO port pins by programming the
GPIODIR
register. A write of a 1
indicates output and a write of a 0 indicates input.
3.
Configure the
GPIOAFSEL
register to program each bit as a GPIO or alternate pin. If an alternate
pin is chosen for a bit, then the
PMCx
field must be programmed in the
GPIOPCTL
register for
the specific peripheral required. There are also two registers,
GPIOADCCTL
and
GPIODMACTL
,
which can be used to program a GPIO pin as a ADC or μDMA trigger, respectively.
4.
Set the
EDMn
field in the
GPIOPC
register as shown in Table 10-3 on page 753.
5.
Set or clear the
GPIODR4R
register bits as shown in Table 10-3 on page 753.
6.
Set or clear the
GPIODR8R
register bits as shown in Table 10-3 on page 753.
7.
Set or clear the
GPIODR12R
register bits as shown in Table 10-3 on page 753.
753
June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller