Texas Instruments TLV320DAC3203, Справочное руководство

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MHz 20
P
CLKIN _ PLL
MHz 10
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MHz 20
P
CLKIN _ PLL
kHz 512
£ £
PLL _ CLKIN R J.D
PLL _ CLK
P
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www.ti.com Clock Generation and PLL
2.7.1 PLL
The TLV320DAC3203 has an on-chip PLL to generate the clock frequency for the audio ADC, DAC, and
Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of
clocks that may be available in the system.
The PLL input supports clocks varying from 512kHz to 20MHz and is register programmable to enable
generation of required sampling rates with fine resolution. The PLL can be turned on by writing to Page 0,
Register 5, D(7). When the PLL is enabled, the PLL output clock PLL_CLK is given by the following
equation:
(17)
R = 1, 2, 3, 4
J = 1, 2, 3, 4,… 63, and D = 0, 1, 2, 3, 4, … 9999
P = 1, 2, 3, 4, … 8
R, J, D, and P are register programmable.
The PLL can be programmed via Page 0, Registers 5-8. The PLL can be turned on via Page 0, Register
5, D(7). The variable P can be programmed via Page 0, Register 5, D(6:4). The default register value for P
is 1, and for J is 4. The variable R can be programmed via Page 0, Register 5, D(3:0). The default register
value for R is 1. The variable J can be programmed via Page 0, Register 6, D(5:0). The variable D is 12-
bits, programmed into two registers. The MSB portion can be programmed via Page 0, Register 7, D(5:0),
and the LSB portion is programmed via Page 0, Register 8, D(7:0). The default register value for D is 0.
When the PLL is enabled the following conditions must be satisfied
• When the PLL is enabled and D = 0, the following conditions must be satisfied for PLL_CLKIN:
(18)
• When the PLL is enabled and D ≠ 0, the following conditions must be satisfied for PLL_CLKIN:
(19)
In the TLV320DAC3203 the PLL_CLK supports a wide range of output clock, based on register settings
and power-supply conditions.
Table 2-22. PLL_CLK Frequency Range
AVdd PLL Mode Min PLL_CLK Max PLL_CLK
Page 0, Reg 4, D6 frequency (MHz) frequency (MHz)
≥ 1.5V 0 80 103
1 95 110
≥
1.65V 0 80 118
1 92 123
≥ 1.80V 0 80 132
1 92 137
The PLL can be powered up independently from the ADC and DAC blocks, and can also be used as a
general purpose PLL by routing its output to the GPIO output. After powering up the PLL, PLL_CLK is
available typically after 10ms. The PLL output frequency is controlled by J.D and R dividers
PLL Divider Bits
J Page 0, Register 6, D(5:0)
D Page 0, Register 7, D(5:0) && Page 0, Register 8, D(7:0)
R Page 0, Register 5, D(3:0)
65 SLAU434 – May 2012 TLV320DAC3203 Application
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