Texas Instruments Tiva TM4C123GH6PM, Руководство пользователя

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System Control
18 System Control
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
18.1 Introduction
System control determines the overall operation of the device. It controls the clocking of the device,
the set of peripherals that are enabled, configuration of the device and its resets, and provides
information about the device.
The device has a set of read-only registers that indicate the size of the memories, the peripherals
that are present, and the pins that are present for peripherals that have a varying number of pins.
This information can be used to write adaptive software that will run on more than one device.
The device can be clocked from one of five sources: an external oscillator, the main oscillator, the
internal oscillator, the internal oscillator divided by four, or the PLL. The PLL can use any of the four
oscillators as its input. When using the PLL, the input clock frequency is constrained to specific
frequencies between 5 MHz and 25 MHz (that is, the standard crystal frequencies in that range).
When direct clocking with an external oscillator or the main oscillator, the frequency is constrained
to between 0 Hz and 80 MHz (depending on the device). The internal oscillator is 16 MHz, +/- 1%;
its frequency will vary by device, with voltage, and with temperature.
Three modes of operation are supported: run mode, sleep mode, and deep-sleep mode. In run
mode, the processor is actively executing code. In sleep mode, the clocking of the device is un-
changed but the processor no longer executes code (and is no longer clocked). In deep-sleep
mode, the clocking of the device may change (depending upon the run mode clock configuration)
and the processor no longer executes code (and is no longer clocked). An interrupt will return the
device to run mode from one of the sleep modes; the sleep modes are entered upon request from
the code.
There are several system events that, when detected, will cause system control to reset the device.
These events are the input voltage dropping too low, the LDO voltage dropping too low, an external
reset, a software reset request, and a watchdog timeout. The properties of some of these events
can be configured, and the reason for a reset can be determined from system control.
Each peripheral in the device can be individually enabled, disabled, or reset. Additionally, the set
of peripherals that remain enabled during sleep mode and deep-sleep mode can be configured,
allowing custom sleep and deep-sleep modes to be defined. Care must be taken with deep-sleep
mode, though, since in this mode the PLL is no longer used and the system is clocked by the input
crystal. Peripherals that depend upon a particular input clock rate (such as a timer) will not operate
as expected in deep-sleep mode due to the clock rate change; these peripherals must either be
reconfigured upon entry to and exit from deep-sleep mode, or simply not enabled in deep-sleep
mode.
There are various system events that, when detected, will cause system control to generate a
processor interrupt. These events are the PLL achieving lock, the internal LDO current limit being
exceeded, the internal oscillator failing, the main oscillator failing, the input voltage dropping too
low, the internal LDO voltage dropping too low, and the PLL failing. Each of these interrupts can
be individually enabled or disabled, and the sources must be cleared by the interrupt handler when
they occur.
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