Texas Instruments TIDA-010046, Руководство по конструкции

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MAC
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DP83825
In
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MI
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Interrupt
RMII (Master/Slave)
MDC, MDIO
Ref Clock: 50 MHz
Media Interface
(MDI)
MAG
N
ET
IC
S
R
J
-4
5
Media Types
-100BASE-TX
-10BASE-Te
AVDD :3.3V
VDDIO:3.3/1.8V
25 MHz XTAL/Ref
Clock 25/50 MHz
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System Overview
13 TIDUES1A – October 2019 – Revised February 2020
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Copyright © 2019–2020, Texas Instruments Incorporated
EMC Compliant 10/100-Mbps Ethernet PHY Reference Design With IEEE
802.3at Type-1 ( ≤ 12.95 W) PoE-PD
Figure 8. DP83825I Schematic for Bootstrap Settings on PD Side Board
2.4.4 Termination Resistors
The DP83822I device has a built-in adjustable series termination network on MAC interface to eliminate
the need for external series termination resistors. The series termination can be adjusted by accessing the
IO MUX GPIO control register (IOCTRL Register, 0x0461). MAC impedance control bits [4:1] allow for a
range of termination adjustments: 42.5
Ω to 99.25 Ω .
The DP83825I device offers programmable termination impedance for RMII interface and integrated MDI
termination resistors as
Figure 9 shows. These features allow the removal of external series termination
resistors. The series termination on the MAC interface can be adjusted by accessing the
IO_CFG_Register register (Offset = 0x302). MAC impedance control bits [15:14] allow termination
adjustments for either 50
Ω or 25 Ω .
Figure 9. Integrated Termination Resistors on RMII and MAC Interfaces of DP83825I
2.4.5 Power and Ground
The device supply pins should be bypassed with low impedance 10-nF, 100-nF, and 1-µF surface mount
capacitors. A 10.0-µF capacitor should also be placed near the PHY component for local bulk bypassing
between the supply and ground planes. To reduce EMI, place the capacitors as close as possible to the
device supply pins, preferably between the supply pins and the vias connecting to the power plane. In
some systems, it may be desirable to add 0-
Ω
resistors in series with supply pins, as the resistor pads
provide flexibility if adding EMI beads becomes necessary to meet system-level certification testing
requirements as
Figure 10 shows.