GND_1
TD_OUT_M
TD_OUT_P
825_TX_EN
825_TX_D0
825_TX_D1
GND_1
RD_OUT_M
RD_OUT_P
825_RX_D0
825_RX_D1
825_RX_DV
825_VDDA3V3
MDIO
MDC
825_LED_0
GND_1
RST
PWRDWN
825_LED_2
825_CLK_IN
2.49k
R46
6.49k
R53
2
1
S2
+3V3_IO
+3V3_IO
1
3
4
2
G
G
25 MHz
Y3
GND_1
0
R59
0
R57
0
R55
DNP
GND_1
2.2k
R48
2.49k
R39
2.49k
R83
DNP
2.49k
R82
DNP
RX_ER
2.49k
R84
DNP
2.49k
R81
DNP
0
R41
DNP
825_CLKOUT
0
R38
825_XIN
825_XOUT
TX_EN
1
CLKOUT_50MHZ/LED_2
2
INT/POWERDOWN
3
LED_0(3V3 AWAYS) /S(A-NEG)
4
RST
5
VDDA3.3
6
RD_M
7
RD_P
8
GND
9
TD_M
10
TD_P
11
XO
12
XI/50MHZ IN
13
RBIAS
14
MDIO
15
MDC
16
RX_D1/S(MASTER/SLAVE)
17
RX_D0/S(PHYADD[1])
18
VDDIO
19
CRS_DV/S(PHYADD[0])
20
GND
21
RX_ER/S(A-MDIX)
22
TX_D0
23
TX_D1
24
DAP
25
DP83825IRMQR
U9
1µF
C42
470
R61
+3V3_825_IO
22pF
C46
22pF
C50
RX_D3/PHYAD4/CLKOUT
1
TX_CLK
2
TX_EN
3
TX_D0
4
TX_D1
5
TX_D2
6
TX_D3
7
INT/PWDN
8
RD_M
9
RD_P
10
TD_M
11
TD_P
12
NC
13
AVD33
14
NC
15
RBIAS
16
LED_0/AN_0/MLED
17
RESET
18
MDIO
19
MDC
20
VDDIO
21
XO
22
XI
23
CLK_O
24
RX_CLK
25
RX_DV/MII_MODE
26
CRS/CRS_DV/LED_CFG
27
RX_ER/AMDIX_EN
28
COL/PHYAD0/MLED
29
RX_D0/PHYAD1
30
RX_D1/PHYAD2
31
RX_D2/PHYAD3
32
PAD
33
U7
DP83822RHBR
GND_1
TD_IN_P
TD_IN_M
RD_IN_P
RD_IN_M
Green
1
2
D8
MDC
MDIO
822_TX_EN
822_TX_D0
822_TX_D1
822_RX_D0
822_RX_D1
822_RX_DV
GND_1
RESET
822_AVD3V3
1
3
4
2
G
G
25 MHz
Y2
DNP
12pF
C36
DNP
12pF
C32
DNP
GND_1
GND_1
2.49k
R25
2.49k
R21
470
R18
2.49k
R91
DNP
GND_1
822_XIN
822_XOUT
4.87k
R23
822_CLK_O
2
1
S1
+3V3_822_IO
+3V3_IO
+3V3_IO
+3V3_IO
GND_1
0
R31
DNP
0
R28
DNP
0
R37
2.2k
R22
825_CLKOUT
1µF
C24
470
R15
5.76k
R85
DNP
2.49k
R93
DNP
GND_1
5.76k
R87
DNP
2.49k
R94
DNP
GND_1
5.76k
R88
DNP
2.49k
R95
DNP
GND_1
5.76k
R89
DNP
2.49k
R96
DNP
GND_1
+3V3_IO
5.76k
R90
DNP
2.49k
R92
DNP
GND_1
LED_1
2.49k
R86
System Overview
12
TIDUES1A – October 2019 – Revised February 2020
Copyright © 2019–2020, Texas Instruments Incorporated
EMC Compliant 10/100-Mbps Ethernet PHY Reference Design With IEEE
802.3at Type-1 (
≤
12.95 W) PoE-PD
Figure 6. DP83822I Schematic for Bootstrap Settings on PSE Side Board
The DP83825I device is connected with the DP83822I device in back-to-back RMII mode (repeater mode).
Therefore, configure pin 20 (with default function CRS_DV) as RX_DV for repeater mode. This can be
achieved in one of two ways:
•
Pullup resistor R39 (= 2.49 k
Ω
) on strap pin-2 (50MHzOut/LED2/S) as highlighted in
and also
in
•
Set bit-8 of the 0x302 register
Table 5. RMII MAC Mode Strap Table for DP83825I
PIN NAME
STRAP NAME
PIN #
DEFAULT
RX_D1
Master/Slave
17
0
0
RMII Master Mode
1
RMII Slave Mode
50MHzOut/LED2
RX_DV_En
2
0
0
Pin 20 is configured as CRS_DV
1
Pin 20 is configured as RX_DV (for
RMII repeater mode)
Figure 7. DP83825 Schematic for Bootstrap Settings on PSE Side Board
2.4.3.2
Hardware Bootstrap Configuration on PD Side Board
Since the DP83825I device is the only PHY on the PD side board, it operates in its default RMII master
mode. However, all the strap pins have provisions for populating the pullup strap resistors just in case the
device configuration needs to be changed as
shows.