2
3
49.9
IN
±
IN+
10 mA
10 mA
I
DIFF
Complementary
Output DAC
15 pF
72 nH
49.9
14.4 pF
15 pF
49.9
14.4 pF
D2S Input
72 nH
49.9
www.ti.com
Design Considerations
7
SBOU161A – February 2016 – Revised April 2016
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Copyright © 2016, Texas Instruments Incorporated
THS3215EVM and THS3217EVM
The EVM allows for flexibility in the D2S input network configuration. The different options are:
1. In order to reduce the high-frequency noise and distortion components from the previous stage driving
the D2S, a passive RLC filter can be inserted prior to the D2S inputs.
Figure 5
shows an example of a
third-order, 200-MHz, Butterworth filter placed between the DAC output and D2S input. The
THS321xEVM is able to evaluate system performance with similar RLC-filter architectures installed on
the board.
Figure 5. 200-MHz Butterworth Filter Before D2S Inputs
2. In single-supply and ac-coupled applications, use R18 and R19 to install the appropriately-sized, ac-
blocking capacitors (see
Figure 4
). Use the midscale buffer output in conjunction with R56, R11, R5,
and R6 to set the desired dc common-mode voltage for the D2S input.
3. The output of the D2S is fed into the internal, noninverting input pin of the OPS by driving PATHSEL
low through switch CS_SW.
4. Certain applications may require an interstage filter inserted between the D2S and OPS to reduce
overall system noise, and prevent high-frequency harmonics from previous stages propagating to the
OPS output. In such situations, use C26, L8, and C27 to insert a third-order, RLC filter into the signal
path of the THS321x (see
Figure 4
). The output of the filter then drives the external noninverting input
of the OPS, VIN+ (pin 9).
